Programmable logic circuit device having look up table enabling to reduce implementation area

• US 20030001615A1
• Filed: 06/28/2002
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Masahiro Iida
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Iida, Masahiro, Sueyoshi, Toshinori
• Granted Patent: US 6,812,737 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A programmable logic circuit device has a plurality of logic blocks, a plurality of routing wires, a plurality of switch circuits, a plurality of connection blocks, and an I/O block performing an input/output operation with external equipment. The routing wires are connected to each of the logic blocks, the switch circuits are provided at an intersection of each of the routing wires, and the connection blocks are provided between an I/O line of each of the logic blocks and each of the routing wires. Each of the logic blocks has a look up table of M inputs and N outputs, which has a plurality of LUT units; and an internal configuration control circuit controlling an internal configuration of the plurality of LUT units.

Claims

1. A look up table of M inputs and N outputs, comprising:

a plurality of LUT units; and

an internal configuration control circuit controlling an internal configuration of said plurality of LUT units.

2. The look up table as claimed in claim 1, wherein said internal configuration control circuit comprises:

a plurality of selectors selecting I/O signals of said plurality of LUT units; and

a selector control circuit controlling said selectors and defining the internal configuration of said plurality of LUT units.

3. The look up table as claimed in claim 2, wherein said selector control circuit comprises a memory, and controls said plurality of selectors in accordance with data stored in said memory.

4. The look up table as claimed in claim 3, wherein said plurality of selectors include:

an input signal selector provided at an input of at least one of said LUT units to select an input signal; and

an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the data stored in said memory.

5. The look up table as claimed in claim 3, wherein said plurality of selectors include:

an input signal selector provided at an input of at least one of said LUT units to select an input signal; and

an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the input signal.

6. The look up table as claimed in claim 1, wherein said look up table of M inputs and N outputs is a 6-input 3-output look up table.

7. The look up table as claimed in claim 6, wherein said 6-input 3-output look up table comprises eight 3-input 1-output LUT units.

8. The look up table as claimed in claim 6, wherein said 6-input 3-output look up table comprises four 3-input 2-output LUT units.

9. A programmable logic circuit device comprising:

a plurality of logic blocks;

a plurality of routing wires connected to each of said logic blocks;

a plurality of switch circuits provided at an intersection of each of said routing wires;

a plurality of connection blocks provided between an I/O line of each of said logic blocks and each of said routing wires; and

an I/O block performing an input/output operation with external equipment, wherein each of said logic blocks has a look up table of M inputs and N outputs, comprising;

a plurality of LUT units; and

an internal configuration control circuit controlling an internal configuration of said plurality of LUT units.

10. The programmable logic circuit device as claimed in claim 9, wherein said internal configuration control circuit comprises:

a plurality of selectors selecting I/O signals of said plurality of LUT units; and

a selector control circuit controlling said selectors and defining the internal configuration of said plurality of LUT units.

11. The programmable logic circuit device as claimed in claim 10, wherein said selector control circuit comprises a memory, and controls said plurality of selectors in accordance with data stored in said memory.

12. The programmable logic circuit device as claimed in claim 11, wherein said plurality of selectors include:

an input signal selector provided at an input of at least one of said LUT units to select an input signal; and

an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the data stored in said memory.

13. The programmable logic circuit device as claimed in claim 11, wherein said plurality of selectors include:

an input signal selector provided at an input of at least one of said LUT units to select an input signal; and

an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the input signal.

14. The programmable logic circuit device as claimed in claim 9, wherein said look up table of M inputs and N outputs is a 6-input 3-output look up table.

15. The programmable logic circuit device as claimed in claim 14, wherein said 6-input 3-output look up table comprises eight 3-input 1-output LUT units.

16. The programmable logic circuit device as claimed in claim 14, wherein said 6-input 3-output look up table comprises four 3-input 2-output LUT units.

18. The method of configuring a look up table as claimed in claim 17, wherein the I/O signals of said plurality of LUT units are selectively controlled in accordance with data stored in the corresponding look up table.

19. The method of configuring a look up table as claimed in claim 17, wherein an input signal input to at least one of said LUT units and an output signal output from said LUT unit are selectively controlled in accordance with data stored in the corresponding look up table.

20. The method of configuring a look up table as claimed in claim 17, wherein an input signal input to at least one of said LUT units and an output signal output from said LUT unit are selectively controlled in accordance with a predetermined function of the input signal.

17. A method of configuring a look up table of M inputs and N outputs, comprising the steps of:

providing a plurality of LUT units; and

selectively controlling I/O signals of said plurality of LUT units to set a predetermined mode of an internal configuration.