MULTI-GIGABIT-PER-SEC CLOCK RECOVERY APPARATUS AND METHOD FOR OPTICAL COMMUNICATIONS

• US 20030001640A1
• Filed: 06/29/2001
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Sierra Monolithics, Inc. (Semtech Corporation)
• Original Assignee: Sierra Monolithics, Inc. (Semtech Corporation)
• Inventors: Lao, Binneg Y., Pulver, James R., Rowe, David A.
• Granted Patent: US 6,509,801 B1
• Time in Patent Office: Days
• US Class Current: 327/165
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and apparatus for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels are disclosed. The invention includes a phase detector for comparing a data signal and a clock signal, a one shot unit for detecting a data transition, an XOR, a filter, a main charge pump, a compensating charge pump for producing additive or compensating current, and a VCO for generating the clock signal. The phase detector includes multiple D-flip flops. The one shot unit includes a delay unit and an AND gate. The filter includes a resistor, a capacitor and a negative resistance amplifier. The main charge pump includes differential inputs, double outputs, cross-quading resistors, differential NPN input transistors, and a current source. The compensating charge pump includes differential NPN input transistors and a current source. In operation, when there is a data transition and if the clock signal and data signal are out of phase synchronization, then the compensating charge pump will enhance the operation of the main charge pump, and the VCO will speed up or slow down the clock signal depending on whether the clock signal is advanced or retarded in phase compared to the data signal. When there is no data transition, the compensating charge pump will in effect counterbalance the operation of the main charge pump, and the frequency of the clock signal will be maintained at the same level it was at the onset of the no data transition period.

Claims

1. A clock recovery apparatus comprising:

a phase detector for receiving a data signal and a clock signal;

a one-shot coupled to said phase detector;

an XOR coupled to said phase detector and said one shot circuit;

a first charge pump coupled to said phase detector and said XOR;

a second charge pump coupled to said first charge pump and said XOR;

a filter coupled to said first charge pump and said second charge pump; and

a voltage controlled oscillator coupled to said filter and said phase detector, said voltage controlled oscillator for generating said clock signal.

2. A clock recovery apparatus according to claim 1,

wherein said first charge pump includes a first differential amplifier,

wherein said first differential amplifier includes:

a first output node and a second output node;

a first resistor coupled to said first output node;

a first transistor for receiving an input from said phase detector, said first transistor coupled to said first output node;

a second resistor coupled to said second output node;

a second transistor for receiving an input from said phase detector, said second transistor coupled to said second output node and said first transistor; and

a first current source coupled to said first and second transistors,

wherein said second charge pump includes a second differential amplifier,

wherein said second differential amplifier includes;

a third transistor for receiving an input from said XOR, said third transistor coupled to said first output node;

a fourth transistor for receiving an input from said XOR, said fourth transistor coupled to said second output node and said third transistor; and

a second current source coupled to said third and fourth transistors,

wherein said filter is coupled between said first output node and said second output node.

3. A clock recovery apparatus according to claim 1, wherein said first charge pump and said second charge pump include NPN transistors.

4. A clock recovery apparatus according to claim 1, wherein said first charge pump includes cross-quading resistors.

5. A clock recovery apparatus according to claim 1, wherein said first charge pump and said second charge pump include Si and Ge.

6. A clock recovery apparatus according to claim 1, wherein a frequency of said clock signal generated by said voltage controlled oscillator is greater than one GHz.

7. A clock recovery apparatus according to claim 1, wherein a frequency of said clock signal generated by said voltage controlled oscillator is greater than eight GHz.

8. A clock recovery apparatus according to claim 1,

wherein said filter includes negative impedance,

wherein said filter is not directly connected to a ground.

9. A clock recovery apparatus according to claim 1,

wherein said second charge pump produces a current that is added to a current produced by said first charge pump when there is a transition in said data signal and if said data signal and said clock signal are out of phase synchronization,

wherein said second charge pump produces a current that in effect counterbalances a current produced by said first charge pump when there is no transition in said data signal.

10. A differential circuit used for recovering a clock signal from data comprising:

a first differential charge pump having first differential inputs and first double outputs;

a second differential charge pump coupled to said first differential charge pump, said second differential charge pump having second differential inputs and second double outputs;

said first double outputs having a first node and a second node;

said second double outputs having a third node and a fourth node, wherein said first node is coupled to said third node, and said second node is coupled to said fourth node; and

a filter coupled between said first node and said second node,

wherein said filter is not directly connected to a ground,

wherein when there is no data transition, the voltage across said first node and said second node remains substantially unchanged,

wherein when there is a data transition and if said clock signal and said data are out of phase synchronization, then the voltage across said first node and said second node changes.

11. A clock recovery apparatus according to claim 10,

wherein said first differential charge pump includes:

a first resistor coupled to said first node;

a first NPN transistor coupled to said first node;

a second resistor coupled to said second node;

a second NPN transistor coupled to said second node and said first NPN transistor; and

a first current source coupled to said first and second NPN transistors,

wherein said second differential charge pump includes;

a third NPN transistor coupled to said first node;

a fourth NPN transistor coupled to said second node and said third NPN transistor; and

a second current source coupled to said third and fourth NPN transistors.

12. A clock recovery apparatus according to claim 10, wherein said first differential charge pump and second differential charge pump include Si and Ge.

13. A clock recovery apparatus according to claim 10, wherein said first differential charge pump and said second differential charge pump operate at a frequency greater than one GHz.

15. A clock recovery apparatus according to claim 14,

wherein said (c) means includes a main differential charge pump and a compensating differential charge pump,

wherein said main differential charge pump includes said first node and said second node as its output nodes,

wherein said compensating differential charge pump includes said first node and said second node as its output nodes.

16. A clock recovery apparatus according to claim 14, wherein a frequency of said clock signal is greater than two GHz.

18. A clock recovery apparatus according to claim 17, wherein a frequency of said clock signal is greater than two GHz.

20. A clock recovery apparatus according to claim 19 further comprising means for producing a voltage across a filter in response to said first and second currents,

wherein said filter includes a first end and a second end,

wherein when there is no transition in said data, the differential voltage level at said first end and said second end remains substantially unchanged,

wherein when there is a transition in said data and if said data and said clock signal are out of phase synchronization, the differential voltage level at said first end and said second end changes,

wherein a frequency of said clock signal is greater than one GHz.

14. A clock recovery apparatus comprising:

(a) means for comparing a phase of data and a phase of a clock signal;

(b) means for detecting a transition in said data;

(c) means for producing a current through a first path including a first node and a current through a second path including a second node;

(d) means for changing the voltage across said first node and said second node when there is a data transition and if said clock signal and said data are out of phase synchronization;

(e) means for maintaining a voltage across said first node and said second node when there is no data transition;

(f) means for speeding up said clock signal when there is a transition in said data and if said clock signal is retarded in phase compared to said data;

(g) means for slowing down said clock signal when there is a transition in said data and if said clock signal is advanced in phase compared to said data; and

(h) means for maintaining a frequency of said clock signal when there is no transition in said data.

17. A clock recovery apparatus comprising:

(a) means for comparing a phase of data and a phase of a clock signal;

(b) means for detecting a transition in said data;

(c) means for producing a voltage across a double-ended filter;

(d) means for providing positive impedance coupled to said double-ended filter;

(e) means for providing negative impedance coupled to said double-ended filter; and

(f) means for providing said clock signal in response to said voltage.

19. A clock recovery apparatus comprising:

(a) means for comparing a phase of data and a phase of a clock signal;

(b) means for detecting a transition in said data;

(c) means for producing a first current;

(d) means for producing a second current;

(e) means for adding said second current to said first current when there is a transition in said data and if said data and said clock signal are out of phase synchronization;

(f) means for counterbalancing said second current with said first current when there is no transition in said data; and

(g) means for generating said clock signal in response to said first and second currents.

21. A clock recovery apparatus comprising:

a phase detector for comparing data and a clock signal;

a control circuit for detecting a transition in said data, said control circuit coupled to said phase detector;

a first charge pump for producing a first current, said first charge pump coupled to said phase detector; and

a second charge pump for producing a second current, said second charge pump coupled to said control circuit and said first charge pump,

wherein a frequency of said clock signal is increased when there is a transition in said data and if said clock signal is retarded in phase compared to said data,

wherein the frequency of said clock signal is decreased when there is a transition in said data and if said clock signal is advanced in phase compared to said data,

wherein the frequency of said clock signal is substantially unchanged when there is no transition in said data.

22. A clock recovery apparatus according to claim 21, wherein the frequency of said clock signal is greater than one GHz.

23. A clock recovery apparatus according to claim 21 further comprising:

a filter coupled to said first charge pump;

a voltage controlled oscillator for generating said clock signal, said voltage controlled oscillator coupled to said filter.

25. A method according to claim 24,

wherein said steps of (d) and (e) further comprising:

adding said first current to said second current when there is a transition in said data and if said clock signal and data are out of phase synchronization;

compensating said first current with said second current when there no transition in said data.

26. A method according to claim 24,

wherein said steps of (d) and (e) further comprising:

producing a charging current to a first node of a filter connected between said first current path and said second current path when there is a data transition and if said clock signal is behind in phase compared to said data;

producing a discharging current to a second node of said filter when there is a data transition and if said clock signal is ahead in phase compared to said data;

producing a change in the differential voltage across said filter when there is a data transition and if said clock signal and said data are out of phase synchronization;

producing no charging or discharging current to said filter when there is no data transition; and

maintaining the differential voltage across said filter during a no data transition period.

27. A method according to claim 24 further comprising:

producing negative impedance.

28. A method according to claim 24, wherein a frequency of said clock signal is greater than two GHz.

24. A method for recovering a clock signal, said method comprising:

(a) receiving data and a clock signal;

(b) detecting a transition in said data;

(c) comparing a phase of said data and a phase of said clock signal;

(d) producing a first current through a first current path,

(e) producing a second current through a second current path,

(f) speeding up said clock signal when there is a transition in said data and if said clock signal is retarded in phase compared to said data;

(g) slowing down said clock signal when there is a transition in said data and if said clock signal is advanced in phase compared to said data; and

(h) maintaining a frequency of said clock signal when there is no transition in said data.