Level shifter

• US 20030001655A1
• Filed: 12/27/2001
• Published: 01/02/2003
• Est. Priority Date: 06/28/2001
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jeong, Jong Bae
• Application Number:
  US10/026,927
• Publication Number:
  US 20030001655A1
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356147 using pass gates

Abstract

The present invention relates to a level shifter. The level shifter comprise a first transistor turned on by a control signal, for transmitting Vcc to a first node; a second transistor turned on by the control signal, for transmitting a zero voltage level to the first node; a third transistor turned on by the Vcc, for transmitting the voltage level of the first node to a second node; a fourth transistor turned by the zero voltage level, for transmitting the voltage level of the first node to a third node; a fifth transistor turned on by the voltage level of the second node, for transmitting a first voltage level to an output; and a sixth transistor turned on by the voltage level of the third node, for transmitting a second voltage level to the output.

Claims

1. A level shifter, comprising:

a first transistor turned on by a control signal, for transmitting Vcc to a first node;

a second transistor turned on by said control signal, for transmitting a zero voltage level to said first node;

a third transistor turned on by said Vcc, for transmitting the voltage level of said first node to a second node;

a fourth transistor turned by said zero voltage level, for transmitting the voltage level of said first node to a third node;

a fifth transistor turned on by the voltage level of said second node, for transmitting a first voltage level to an output; and

a sixth transistor turned on by the voltage level of said third node, for transmitting a second voltage level to said output.

2. The level shifter as claimed in claim 1, wherein said first, fourth and fifth transistors are formed of a PMOS transistor.

3. The level shifter as claimed in claim 1, wherein said second, third and sixth transistors are formed of a NMOS transistor.

4. The level shifter as claimed in claim 1, further including a seventh transistor turned when said output is VPPX, for making the voltage level of said third node completely a zero voltage level.

5. The level shifter as claimed in claim 4, wherein said seventh transistor is formed of a NMOS transistor.

6. The level shifter as claimed in claim 1, further including an eighth transistor turned when said output is VEEX, for making the voltage level of said second node a Vcc state.

7. The level shifter as claimed in claim 6, wherein said eighth transistor is formed of a PMOS transistor.