Semiconductor device

• US 20030001658A1
• Filed: 07/24/2002
• Published: 01/02/2003
• Est. Priority Date: 11/28/2000
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Matsumoto, Koichi
• Application Number:
  US10/181,999
• Publication Number:
  US 20030001658A1
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Disclosed is a MOS-type semiconductor apparatus which adjusts the threshold voltage to a predetermined value, and lowers leak current and reduces power consumption without lowering the operating speed of transistors. The MOS-type semiconductor apparatus (1) formed using an SOI substrate in which a support substrate (3), an insulation layer (buried oxide film) (2), and a semiconductor layer are sequentially layered comprises conductors (N-wells and P-wells) beneath the insulation layer (2), and a threshold-value control circuit which compares a signal f (soi) generated by an oscillator in the semiconductor apparatus to a reference signal f (ref) inputted from outside, and applies bias voltages V_sub1 and V_sub2 to the conductors (the N-wells and P-wells) based on the difference between both signals.

Claims

1. A semiconductor apparatus which is a MOS-type semiconductor apparatus formed using an SOI substrate formed with a support substrate, an insulation layer, and a semiconductor layer sequentially layered, comprising:

a conductor beneath said insulation layer; and

a threshold-value control circuit which compares signals generated by an oscillator in said semiconductor apparatus to a reference signal inputted from outside, and applies a bias voltage to said conductor based on the difference between both signals.

2. The semiconductor apparatus according to claim 1, wherein said conductor beneath said insulation layer includes a well formed by ion implantation to said support substrate.

3. The semiconductor apparatus according to claim 1 or claim 2, wherein said semiconductor apparatus is of a C-MOS (Complementary MOS) type in which both a P-well and an N-well are formed on said support substrate, and a bias voltage is simultaneously applied to said P-well and said N-well.

4. The semiconductor apparatus according to one of claim 1˜

claim 3, wherein a full-depletion type MOS-type transistor is formed.

5. The semiconductor apparatus according to one of claim 1˜

claim 4, further comprising a charge pump circuit for enabling application of a bias voltage at a voltage higher than a power source voltage.