Apparatus, method and system with a graphics-rendering engine having a graphics context manager

• US 20030001848A1
• Filed: 06/29/2001
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sreenivas, Aditya, Doyle, Peter L.
• Granted Patent: US 7,173,627 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: G06F 9/463 Program control block organisation

Abstract

A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

Claims

1. An apparatus, comprising:

a graphics-rendering engine to concurrently render two or more independent images for display on multiple display devices, the two or more independent images include a first independent image and a second independent image; and

a graphics context manager to store in a first memory area and restore from the first memory area information describing a first rendering context associated with the first independent image, the graphics context manager to store in a second memory area and restore from the second memory area information describing a second rendering context associated with the second independent image.

2. The apparatus of claim 1, wherein the graphics context manager further comprises:

a plurality of memory areas, each memory area to store a rendering context associated with the instructions from a particular graphics application, the plurality of memory areas includes the first memory area and the second memory area; and

a plurality of context identification registers including a first context identification register and a second context identification register, the first context identification register contains information to point to an address of the first memory area, the second context identification register contains information to point to an address of the second memory area.

3. The apparatus of claim 2, wherein the graphics context manager further comprises:

a third register to track which memory area in the plurality of memory areas contains the rendering context information to be supplied to the graphics-rendering engine.

4. The apparatus of claim 1, wherein the first memory area is located on the same chip containing the graphics-rendering engine.

5. The apparatus of claim 2, wherein the first context identification register contains a field to assist in switching the first rendering context associated with a two dimensional image to the second rendering context associated with a three dimensional image.

6. The apparatus of claim 2, wherein the first context identification register contains a field to assist in switching the first rendering context associated with a textured-map image to the second rendering context associated with a non-texture-mapped image.

7. The apparatus of claim 2, further comprises:

the first memory area to contain instructions for the two or more independent images in a first instruction stream.

8. The apparatus of claim 2, further comprises:

the first memory area to contain instructions for one or more independent images in a first instruction stream, and the first memory area to contain instructions for one or more independent images in a second instruction stream.

9. The apparatus of claim 1, further comprises:

One or more instruction transports to deliver instructions for the two or more independent images to the graphics-rendering engine, the one or more instruction transports including a first instruction transport.

10. The apparatus of claim 9, wherein each instruction transport is associated with a particular display device.

11. The apparatus of claim 9, wherein the first instruction transport comprises:

an instruction memory area;

a first register to define a start and an end to the instruction memory area; and

a memory access engine to fetch and deliver the instructions from the instruction memory area to the graphics-rendering engine.

12. The apparatus of claim 9, wherein the instruction transport further comprises:

a third memory area to store an independent sequence of instructions that can be invoked from an instruction stream.

13. The apparatus of claim 1, further comprises:

a time allocator to arbitrate the use of the graphics-rendering engine between the two or more independent images.

14. The apparatus of claim 13, wherein the time allocator comprises:

a plurality of registers including a first register, the first register having a plurality of fields, a first field to determine whether the first register participates in an arbitration process to use the graphics rendering engine, a second field to point to a memory location containing instructions from a first instruction stream.

15. The apparatus of claim 13, wherein the time allocator further comprising:

A first module to establish a programmable elapsed period of time to use the graphics-rendering engine, the period of time is defined by a programmable number of unit time periods, where each unit time period is defined by a programmable number of real-time time quanta.

16. The apparatus of claim 14, wherein the time allocator further comprises:

a first module to direct the graphics-rendering engine to process instructions associated with a first independent image, the instructions stored in a first memory area, the first memory area having an address defined by information contained within the plurality of the fields.

18. The method of claim 17, further comprising:

using a timing circuit to allocate the use of the graphics-rendering engine between instructions associated with the first graphics application and instructions associated with the second graphics application.

19. The method of claim 17, further comprising:

including the first memory area and the second memory area in a plurality of memory areas; and

using a volatile memory device to track which memory area in the plurality of memory areas contains the rendering context information to be supplied to the graphics-rendering engine.

20. The method of claim 17, further comprising:

displaying the multiple independent images on a single display device.

17. A method, comprising:

concurrently rendering instructions associated with multiple independent images within a first instruction-stream;

storing in a first memory area information representing a first rendering context associated with a first independent image;

restoring from a second memory area instructions representing a second rendering context associated with a second independent image; and

switching a graphics-rendering engine from the first rendering context to the second rendering context.

21. A system, comprising:

a central processing unit; and

a graphics device, the central processing unit coupled to the graphics device, the graphics device containing a graphics-rendering engine to concurrently render two or more independent images for display on multiple display devices, and a graphics context manager to store in a first memory area and restore from the first memory area information describing a first rendering context associated with the first independent image, the graphics context manager to store in a second memory area and restore from the second memory area information describing a second rendering context associated with the second independent image.

22. The system of claim 21, wherein the graphics device further comprises:

a time allocator to arbitrate the use of the graphics-rendering engine between the two or more independent images.

23. The system of claim 21, wherein the graphics device further comprises:

an instruction transport to deliver instructions for the independent images to the graphics-rendering engine as controlled by the time allocator.