SRAM device

• US 20030002328A1
• Filed: 06/26/2002
• Published: 01/02/2003
• Est. Priority Date: 06/28/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamauchi, Hiroyuki
• Granted Patent: US 6,898,111 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

Claims

1. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner,

wherein the drive transistor and the access transistor of one unit circuit have substantially the same channel width, and the channel width is larger than that of the drive transistor and the access transistor of the other unit circuit.

2. The SRAM device of claim 1, wherein a channel width ratio between the load transistor and the drive transistor of one unit circuit and that of the other unit circuit are different from each other by 15% or more.

3. The SRAM device of claim 1, wherein an inversion threshold level of the inverter of one unit circuit and that of the other unit circuit are different from each other by 30% or more.

4. The SRAM device of claim 1, wherein the two unit circuits are asymmetric with each other in terms of a magnitude of an off leak current of the inverter.

5. The SRAM device of claim 1, wherein the two unit circuits are asymmetric with each other in terms of a thickness of a gate oxide film of the constituent transistors.

6. The SRAM device of claim 1, wherein the two unit circuits are asymmetric with each other in terms of a layout area of the constituent transistors.

7. The SRAM device of claim 1, wherein at least one of a lateral size and a longitudinal size of a layout area of one unit circuit can be determined independently of that of the other unit circuit.

8. The SRAM device of claim 1, wherein the drive transistor and the access transistor are formed in the same continuous active region in each of the two unit circuits.

9. The SRAM device of claim 1, wherein a bit line connected to one of the two unit circuits that has a smaller channel width is used only for write operations, whereas a bit line connected to the other unit circuit is used for both read and write operations.

10. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner,

wherein the two unit circuits are asymmetric with each other in terms of a magnitude of an off leak current of the inverter.

11. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner,

wherein the two unit circuits are asymmetric with each other in terms of a thickness of a gate oxide film of the constituent transistors.

14. The SRAM device of claim 13, wherein the drive transistor and the access transistor have substantially the same channel width in each of the two unit circuits.

12. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner, wherein:

a bit line connected to one of the two unit circuits is used only for write operations, whereas a bit line connected to the other unit circuit is used for both read and write operations;

a current driving power of at least one of the constituent transistors of one of the unit circuits that is connected to the write-only bit line is set to be lower than that of corresponding one of the constituent transistors of the other unit circuit; and

the access transistors of the two unit circuits are configured so that only one of the access transistors is activated during a read operation, whereas both of the access transistors are activated during a write operation.

13. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, a source line connected to the drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner, wherein:

the two unit circuits are asymmetric with each other in terms of a current driving power of the constituent transistors; and

the SRAM device further comprises means for setting, during a read operation, a potential level of the source line of one of the two unit circuits of the lower current driving power to be higher than that of the source line of the other unit circuit.

15. An SRAM device, comprising two unit circuits each including a load transistor, a drive transistor, and an access transistor, wherein the load transistor and the drive transistor together form an inverter and the access transistor connects an output of the inverter to a bit line, with the two unit circuits being coupled to each other by connecting an input and an output of the inverter of one unit circuit with those of the inverter of the other unit circuit in a cross-coupled manner,

wherein in each of the two unit circuits, the drive transistor and the access transistor have substantially the same channel width and are formed in the same continuous rectangular-shaped active region with no bent portions.