OPERATING TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS OF A NON-VOLATILE MEMORY OPERATED IN MULTIPLE DATA STATES

• US 20030002348A1
• Filed: 06/27/2001
• Published: 01/02/2003
• Est. Priority Date: 06/27/2001
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation), SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Tanaka, Tomoharu, Quader, Khandker N., Fong, Yupin
• Granted Patent: US 6,522,580 B2
• Time in Patent Office: Days
• US Class Current: 365/189.01
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

Claims

1. A method of operating a non-volatile memory system wherein values stored in some of storage elements of an array of memory elements affect values read from others of the storage elements because of at least electric field coupling between storage elements, comprising:

writing into a first group of storage elements a first set of stored values that correspond to a first set of data,

thereafter writing into a second group of storage elements different from the first group a second set of stored values that correspond to a second set of data, wherein at least some of the stored second set of values affect values read from at least some of the first group of storage elements because of at least field coupling between them, and

altering the first set of stored values written into the first group of storage elements in order to counteract an effect of the second set of stored values on the values read from said at least some of the first group of storage elements because of at least field coupling between them, thereby to facilitate accurate reading of the first set of data from the first group of storage elements.

2. The method of claim 1, wherein the characteristic of the first set of stored values that is affected by the second set of stored values includes broadening an apparent distribution of those of the stored first set of values that correspond to particular states of the first set of data, and wherein altering the first set of stored values includes compacting the distribution of those of the stored first set of values that correspond to particular states of the first set of data.

3. The method of claim 2, wherein compacting the distribution occurs after writing the second set of stored values.

4. The method of claim 3, additionally comprising, prior to compacting the distribution of the stored first set of values, reading the first set of data from the first group of storage elements.

5. The method of claim 2, wherein compacting the distribution occurs before writing the second set of stored values.

6. The method of any one of claims 1-5, wherein the storage elements are electrically floating gates, and wherein the stored values are charge levels stored on the floating gates that affect conduction through memory cell transistors of which the floating gates are a part.

7. The method of claim 6, wherein more than two stored values are defined for individual ones of the floating gates in order to store more than one bit of data on the individual floating gates.

8. The method of claim 1, wherein the non-volatile memory system in which the operating method is carried out includes an array of flash electrically erasable and programmable read only memory (EEPROM) cells having storage elements in the form of at least one floating gate per cell.

9. The method of claim 8, wherein the non-volatile memory system in which the operating method is carried out includes memory cells having two floating gates per cell.

10. The method of claim 8, wherein the non-volatile memory system in which the operating method is carried out includes memory cells connected in a NAND arrangement.

11. A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, comprising:

programming data into a first plurality of storage elements,

thereafter programming data into a second plurality of storage elements,

thereafter reading data programmed into the first plurality of storage elements, and

thereafter reprogramming the first plurality of storage elements with the read data, whereby the reprogramming is accomplished without having to retain a copy of the data initially programmed into the first plurality of storage elements.

13. The method of claim 12, wherein reprogramming storage levels in one portion of the individual distributions into another portion thereof includes incrementally changing the storage levels of individual storage elements until one of a second set of reference storage levels corresponding to the data being stored is reached or exceeded, the second set of reference storage levels individually being displaced from corresponding ones of the first set of reference storage levels within corresponding distributions.

14. The method of claim 13, wherein an amount of the incremental change of storage levels during programming is greater than that during reprogramming.

15. The method of claim 12, wherein the non-volatile array of storage elements in which the method is carried out includes an array of memory cells having storage elements in the form of at least one floating gate per cell.

16. The method of claim 15, wherein the non-volatile storage elements in which the operating method is carried out includes memory cells having two floating gates per cell.

17. The method of claim 15, wherein the non-volatile storage elements in which the operating method is carried out includes memory cells connected in a NAND arrangement.

12. A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another but where values read from storage elements are affected by values stored by adjacent storage elements because of field coupling between the storage elements, and wherein the individual storage elements are programmed by incrementally changing the storage levels thereof until one of the storage level ranges is reached that corresponds to the data being stored therein, comprising:

programming data into a plurality of the storage elements by incrementally changing the storage levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with a distribution of storage levels among the plurality of storage elements within the defined ranges having widths resulting from incrementally changing the storage levels, and

thereafter reprogramming the storage levels in one portion of individual ones of said distributions into another non-overlapping portion thereof, thereby to reduce the extents of the storage level distributions within the individual defined ranges of storage levels and to increase the separation between the individual defined ranges of storage levels in order to allow for the effects of field coupling between adjacent storage elements.

18. A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, and wherein the individual storage elements are programmed by incrementally changing the storage levels thereof until one of the storage level ranges is reached that corresponds to the data being stored therein, comprising:

programming data into a plurality of the storage elements by incrementally changing the storage levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with distributions of storage levels among the plurality of storage elements within defined ranges having widths resulting from incrementally changing the storage levels, and

thereafter reprogramming those of the storage elements having storage levels in one portion of individual ones of said distributions by incrementally changing the storage levels of those individual storage elements until programmed into another non-overlapping portion of their respective distributions, the amount of incremental change during programming being greater than the incremental change of storage levels during reprogramming.

19. A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, and wherein the individual storage elements are programmed by incrementally changing the storage levels thereof until one of the storage level ranges is reached that corresponds to the data being stored therein, comprising:

programming data into a first plurality of the storage elements by incrementally changing the storage levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with distributions of storage levels among the plurality of storage elements within defined ranges having widths resulting from incrementally changing the storage levels,

thereafter programming data into a second plurality of storage elements,

thereafter reading data programmed into the first plurality of storage elements, and

thereafter reprogramming those of the first plurality of storage elements having storage levels in one portion of individual ones of said distributions with the read data by incrementally changing the storage levels of those individual storage elements until programmed into another non-overlapping portion of their respective distributions, whereby the reprogramming is accomplished without having to retain a copy of the data initially programmed into the first plurality of storage elements.

20. A method of programming at least first and second groups of individual storage elements of a non-volatile memory with two or more data bits in at least two programming steps, wherein coupling exists between adjacent ones of the first and second groups of storage elements that affects bit proportional levels read therefrom, comprising:

programming the first group of storage elements with all of their said two or more data bits before programming the second group of storage elements, and

thereafter, programming the second group of storage elements with all of their said two or more data bits.

21. The method of claim 20, additionally comprising:

reprogramming the first group of storage elements with all of their said two or more bits.

22. The method of claim 21, wherein reprogramming the first group of storage elements includes compacting the bit proportional levels for the individual data bits stored of the first group of storage elements.

23. The method of claim 22, wherein reprogramming the first group of storage elements takes place before programming the second group of storage elements.

24. The method of claim 21, wherein reprogramming the first group of storage elements takes place after programming the second group of storage elements.

25. The method of any one of claims 20-24, wherein the storage elements are electrically floating gates, and wherein the bit proportional levels are charge levels stored on the floating gates that affect conduction through memory cell transistors of which the floating gates are a part.

26. The method of claim 20, wherein the non-volatile memory in which the operating method is carried out includes an array of flash electrically erasable and programmable read only memory (EEPROM) cells having storage elements in the form of at least one floating gate per cell.

27. The method of claim 26, wherein the non-volatile memory system in which the operating method is carried out includes memory cells having exactly two floating gates per cell.

28. The method of claim 26, wherein the non-volatile memory system in which the operating method is carried out includes memory cells connected in a NAND arrangement.

30. The method of claim 29, wherein said first increasing rate is equal to the second increasing rate.

31. The method of claim 29, wherein said first increasing rate is higher than the second increasing rate.

29. In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the memory cell;

b) generating a first verify flag by determining whether the memory cell has reached a preliminary state; and

c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,

2) the second program procedure determining whether the memory cell has reached the given state,

3) the third program procedure, which is exerted on the memory cell if the memory cell has been determined not to have reached the given state, including the steps of;

d) applying a second program voltage to the memory cell;

e) generating a second verify flag by determining whether the memory cell has reached the given state; and

f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

32. The method of any one of claims 29-31, wherein a starting level of the first program voltage is lower than that of the second program voltage.

33. In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the memory cell;

b) generating a fist verify flag by determining whether the memory cell has reached a preliminary state; and

c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,

2) the second program procedure determining whether the memory cell has remained within a specified state not included in the given state,

3) the third program procedure, which is exerted on the memory cell if the memory cell has remained within the specified state, including the steps of;

d) applying a second program voltage to the memory cell;

e) generating a second verify flag by determining whether the memory cell has reached the given state; and

f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

34. The method of claim 33, wherein said first increasing rate is equal to the second increasing rate.

35. The method of claim 33, wherein said first increasing rate is higher than the second increasing rate.

36. The method of any one of claims 33-35, wherein a starting level of the first program voltage is lower than that of the second program voltage.

40. The method of claim 39, wherein a starting level of the second program voltage is higher than that of the third program voltage.

41. The method of claim 39, wherein said first, second and third increasing rates are the same.

42. The method of claim 39, wherein said second increasing rate is higher than the first increasing rate, and the first increasing rate is equal to the third increasing rate.

37. In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the memory cell;

b) generating a fist verify flag by determining whether the memory cell has reached a preliminary state; and

c) continuing to apply the first program voltage to the memory cell if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,

2) the second program procedure determining whether the memory cell has reached the given state,

3) the third program procedure, which is exerted on the memory cell if the memory cell has been determined not to have reached the given state, including the steps of;

d) applying a second program voltage to the memory cell;

e) generating a second verify flag by determining whether the memory cell has reached the given state; and

f) continuing to apply the second program voltage to the memory cell if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

38. In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the memory cell;

b) generating a fist verify flag by determining whether the memory cell has reached a preliminary state; and

c) continuing to apply the first program voltage to the memory cell if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,

2) the second program procedure determining whether the memory cell has remained within a specified state not included in the given state,

3) the third program procedure, which is exerted on the memory cell if the memory cell has remained within the specified state, including the steps of;

d) applying a second program voltage to the memory cell;

e) generating a second verify flag by determining whether the memory cell has reached the given state; and

f) continuing the second program voltage to the memory cell if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

39. In a memory array including first and second memory cells, a method of programming the first and second memory cells to a given state, the second memory cell being programmed after programming the first memory cell, the method comprising first, second, third and fourth program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the first memory cell;

b) generating a fist verify flag by determining whether the first memory cell has reached a preliminary state; and

c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the first memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the first memory cell,

2) the second program procedure determining whether the first memory cell has reached the given state,

3) the third program procedure, which is exerted on the first memory cell if the first memory cell has been determined not to have reached the given state, including the steps of;

d) applying a second program voltage to the first memory cell;

e) generating a second verify flag by determining whether the first memory cell has reached the given state; and

f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the first memory cell has not reached to the given state, otherwise removing the second program voltage from the first memory cell,

4) the fourth program procedure, which is exerted on the second memory cell after the first, second and third program procedures, including the steps of;

g) applying a third program voltage to the second memory cell;

h) generating a third verify flag by determining whether the second memory cell has reached the given state; and

i) increasing the third program voltage with a third increasing rate if the third verify flag indicates that the second memory cell has not reached to the given state, otherwise removing the third program voltage from the second memory cell.

43. The method of any one of claims 39-42, wherein a starting level of the first program voltage is lower than that of the second program voltage, and is equal to that of the third program voltage.

44. In a memory array including first and second memory cells, a method of programming the first and second memory cells to a given state, the second memory cell being programmed after programming the first memory cell, the method comprising first, second, third and fourth program procedures, the first program procedure including the steps of:

a) applying a first program voltage to the first memory cell;

b) generating a fist verify flag by determining whether the first memory cell has reached a preliminary state; and

c) continuing to apply the first program voltage to the first memory cell if the first verify flag indicates that the first memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the first memory cell,

2) the second program procedure determining whether the first memory cell has reached the given state,

3) the third program procedure, which is exerted on the first memory cell if the first memory cell has been determined not to have reached the given state, including the steps of;

d) applying a second program voltage to the first memory cell;

e) generating a second verify flag by determining whether the first memory cell has reached the given state; and

f) continuing to apply the second program voltage to the first memory cell if the second verify flag indicates that the first memory cell has not reached to the given state, otherwise removing the second program voltage from the first memory cell,

4) the fourth program procedure, which is exerted on the second memory cell after the first, second and third program procedures, including the steps of;

g) applying a third program voltage to the second memory cell;

h) generating a third verify flag by determining whether the second memory cell has reached the given state; and

i) continuing to apply the third program voltage to the second memory cell if the third verify flag indicates that the second memory cell has not reached to the given state, otherwise removing the third program voltage from the second memory cell.