Process for manufacturing a DMOS transistor

• US 20030003669A1
• Filed: 06/11/2002
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Graf, Michael, Dietz, Franz, Dudek, Volker, Bromberger, Christoph, Klaussner, Manfred, Herrfurth, Joern
• Granted Patent: US 6,878,603 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.

According to the new process, it is possible in the case of a trench-shaped structure to set the doping of the side walls independently from the doping of the floor region. Furthermore, it is also possible to set different dopings among the side walls. For DMOS transistors, this allows high breakthrough voltages to be generated even with low turn-on resistances, and the space requirement, in particular with regard to driver structures, can be reduced.

Claims

1. Process for manufacturing a DMOS transistor (100) with a semiconductor body (5),

which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type and a first well region (20) of a first conductivity type, enclosing the source region (10), and

a gate region (35) being formed on the surface of the surface layer of the semiconductor body (5), which gate region—

starting at the source region (10)—

extends across at least part of the well region (20), wherein

starting on the surface of the semiconductor body (5) in the surface layer, a trench-shaped structure is produced, and wherein

in the floor region (50) of the trench-shaped structure a doping of the second conductivity type is produced with a first concentration value, and wherein

in the source-end side wall (40) of the trench-shaped structure a doping of the second conductivity type is produced with a second concentration value, and wherein

in the drain-end side wall (60) of the trench-shaped structure a doping of the second conductivity type is produced with a third concentration value.

2. Process according to claim 1 wherein the trench-shaped structure is produced partially or wholly within the well region (20).

3. Process according to claim 2 wherein the well region (20) encloses the drain region (80).

4. Process according to claim 1 wherein, below the drain region (80), an extension region (70) of a second conductivity type is produced which encloses the drain region (80).

5. Process according to claim 3 wherein, below the drain region (80), an extension region (70) of a second conductivity type is produced which encloses the drain region (80).

6. Process according to claim 1 wherein the drain region (80) is produced immediately adjacent to a side wall of the trench-shaped structure.

7. Process according to claim 5 wherein the drain region (80) is produced immediately adjacent to a side wall of the trench-shaped structure.

8. Process according to claim 5 wherein the extension region (70) is produced immediately adjacent to a side wall of the trench-shaped structure.

9. Process according to claim 5 wherein the drain region (80) and the extension region (70) are produced immediately adjacent to a side wall of the trench-shaped structure.

10. Process according to claim 5 wherein a distance between the side wall of the trench-shaped structure and the extension region (70) is produced which is preferably between 0.5 μ

m and 4.0 μ

m.

11. Process according to claim 1 wherein a distance between the side wall of the trench-shaped structure and the drain region (80) is produced which is preferably between 0.5 μ

m and 4.0 μ

m.

12. Process according to claim 5 wherein a distance between the side wall of the trench-shaped structure and the drain region (80) is produced which is preferably between 0.5 μ

m and 4.0 μ

m.

13. Process according to claim 5 wherein a distance between the side wall of the trench-shaped structure on the one hand and the extension region (70) and the drain region (80) on the other hand, is produced which is preferably between 0.5 μ

m and 4.0 μ

m.

14. Process according to claim 1 wherein—

in the side walls and in the floor region (50) of the trench-shaped structure—

a doping is produced which features a higher concentration level than in the semiconductor body (5) and/or the well region (20).

15. Process according to claim 9 wherein—

in the side walls and in the floor region (50) of the trench-shaped structure—

a doping is produced which features a higher concentration level than in the semiconductor body (5) and/or the well region (20).

16. Process according to claim 13 wherein—

in the side walls and in the floor region (50) of the trench-shaped structure—

a doping is produced which features a higher concentration level than in the semiconductor body (5) and/or the well region (20).

17. Process according to claim 1 wherein a trench-shaped structure is produced, with the second and third doping agent concentration values being equal.

18. Process according to claim 9 wherein a trench-shaped structure is produced, with the second and third doping agent concentration values being equal.

19. Process according to claim 13 wherein a trench-shaped structure is produced, with the second and third doping agent concentration values being equal.

20. Process according to claim 1 wherein a trench-shaped structure is produced, with the second doping agent concentration value being lower than the third doping agent concentration value.

21. Process according to claim 9 wherein a trench-shaped structure is produced, with the second doping agent concentration value being lower than the third doping agent concentration value.

22. Process according to claim 13 wherein a trench-shaped structure is produced, with the second doping agent concentration value being lower than the third doping agent concentration value.

23. Process according to claim 1 wherein a trench-shaped structure is produced whose aspect ratio is above 0.5 and whose width is within a range between 0.5 μ

m and 4.0 μ

m.

24. Process according to claim 1 wherein a trench-shaped structure is produced, which features a narrower width in the floor region (50) than on the surface.

25. Process according to claim 1 wherein the trench-shaped structure is produced by STI etching and filled with an isolating material, preferably by means of an oxide.

26. Process according to claim 1 wherein the trench-shaped structure is produced by means of a LOCOS oxidation.

27. Process according to claim 1 wherein the semiconductor body features an isolating intermediate layer (4) below the surface layer, and the DMOS transistor is produced in the surface layer.

28. Process according to claim 27 wherein the thickness of the surface layer underneath the trench-shaped structure is within a range between one half and a factor 5 of the depth of the trench-shaped structure.

29. Process according to claim 1 wherein the thickness of the surface layer underneath the trench-shaped structure is within a range between one half and a factor 5 of the depth of the trench-shaped structure.

30. Process according to claim 27 wherein the drain region (80) and/or the extension region (70) as well as the well region (20), and the source region (10), are produced immediately adjacent to the isolating intermediate layer (4).