Vertical electronic circuit package and method of fabrication therefor

• US 20030003705A1
• Filed: 07/02/2001
• Published: 01/02/2003
• Est. Priority Date: 07/02/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sankman, Robert L., Figueroa, David G., Chung, Chee-Yee
• Granted Patent: US 6,555,920 B2
• Time in Patent Office: Days
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/0919 : Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
• CPC Class Codes: H05K 2201/10446 : Mounted on an edge
• CPC Class Codes: H05K 2201/10454 : Vertically mounted
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/366 : substantially perpendicularly to each other H05K3/361 takes precedence

Abstract

An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section'"'"'s horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section'"'"'s horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Claims

1. An electronic circuit package comprising:

a vertical package section, which includes multiple first conductive layers separated by multiple first dielectric layers, wherein the multiple first conductive layers and the multiple first dielectric layers are oriented in parallel with a vertical plane, and wherein a top surface and a bottom surface of the vertical package section are parallel with a horizontal plane that is perpendicular to the vertical plane;

a first set of bond pads located on the top surface of the vertical package section and electrically connected to the multiple first conductive layers; and

a second set of bond pads located on the bottom surface of the vertical package section and electrically connected to the multiple first conductive layers.

2. The electronic circuit package as claimed in claim 1, further comprising conductive structures that electrically connect one or more of the multiple first conductive layers with one or more side surfaces of the vertical package section, wherein the conductive structures are connectable to one or more discrete capacitors.

3. The electronic circuit package as claimed in claim 1, further comprising:

a horizontal package section, which includes multiple second conductive layers separated by multiple second dielectric layers, wherein the multiple second conductive layers, the multiple second dielectric layers, a top surface, and a bottom surface of the horizontal package section are oriented in parallel with the horizontal plane;

a third set of bond pads located on the top surface of the horizontal package section and electrically connected to the second set of bond pads and to the second conductive layers; and

a set of connectors located on the bottom surface off the horizontal package section and electrically connected to the second conductive layers.

4. The electronic circuit package as claimed in claim 3, wherein the set of connectors are a fourth set of bond pads.

5. The electronic circuit package as claimed in claim 3, wherein the set of connectors are a set of pins.

6. The electronic circuit package as claimed in claim 3, further comprising conductive structures that electrically connect one or more of the multiple second conductive layers with the top surface of the horizontal package section, wherein the conductive structures are connectable to one or more discrete capacitors.

7. The electronic circuit package as claimed in claim 6, wherein the conductive structures accomplish a pitch conversion, along a first direction, between a first pitch of the third set of bond pads to a second pitch of the fourth set of bond pads, and wherein the second pitch is larger than the first pitch.

8. The electronic circuit package as claimed in claim 1, wherein a set of the multiple conductive layers form substantially planar areas of conductive material, and the set of the multiple conductive layers are used to conduct power or ground.

9. The electronic circuit package as claimed in claim 8, wherein at least some of the set of the multiple conductive layers are outside layers of the vertical package section.

10. The electronic circuit package as claimed in claim 1, wherein a set of the multiple conductive layers form traces of conductive material, wherein each trace is used to conduct an input/output signal, and each trace interconnects one bond pad of the first set of bond pads with one pad of the second set of bond pads.

11. The electronic circuit package as claimed in claim 10, wherein the traces of conductive material accomplish a pitch conversion, along a first direction, between a first pitch of the first set of bond pads to a second pitch of the second set of bond pads, and wherein the second pitch is larger than the first pitch.

12. The electronic circuit package as claimed in claim 10, wherein at least some of the set of the multiple conductive layers are inside layers of the vertical package section, and one or more outside layers of the vertical package section are used to conduct power or ground.

13. The electronic circuit package as claimed in claim 1, wherein the vertical package section is formed from organic printed circuit materials.

14. The electronic circuit package as claimed in claim 1, wherein the vertical package section is formed from ceramic printed circuit board materials.

15. The electronic circuit package as claimed in claim 1, wherein the first set of bond pads is connectable to one or more complementary sets of bond pads on one or more integrated circuits.

16. The electronic circuit package as claimed in claim 15, wherein the first set of bond pads is connectable to a complementary set of bond pads on a microprocessor.

18. The method as claimed in claim 17, wherein forming the first set of bond pads comprises:

selectively plating the top surface of the vertical package section.

19. The method as claimed in claim 17, further comprising:

electrically connecting, through conductive structures, one or more of the multiple first conductive layers with one or more side surfaces of the vertical package section, wherein the conductive structures are connectable to one or more discrete capacitors.

20. The method as claimed in claim 17, further comprising:

fabricating a horizontal package section, which includes multiple second conductive layers separated by multiple second dielectric layers, wherein the multiple second conductive layers, the multiple second dielectric layers, a top surface, and a bottom surface of the horizontal package section are oriented in parallel with the horizontal plane;

forming a third set of bond pads located on the top surface of the horizontal package section and electrically connected to the second set of bond pads and to the second conductive layers; and

electrically connecting the second set of bond pads with the third set of bond pads.

21. The method as claimed in claim 20, further comprising:

electrically connecting, through conductive structures, one or more of the multiple second conductive layers with the top surface of the horizontal package section, wherein the conductive structures are connectable to one or more discrete capacitors.

22. The method as claimed in claim 17, wherein the electronic circuit package is an integrated circuit package, the method further comprising electrically connecting one or more integrated circuits to the integrated circuit package.

24. The electronic system as claimed in claim 23, further comprising:

one or more discrete capacitors electrically connected to conductive structures, which electrically connect one or more of the multiple first conductive layers with one or more side surfaces of the vertical package section.

25. The electronic system as claimed in claim 23, wherein the integrated circuit package further comprises:

a horizontal package section having multiple second conductive layers separated by multiple second dielectric layers, wherein the multiple second conductive layers, the multiple second dielectric layers, a top surface, and a bottom surface of the horizontal package section are oriented in parallel with the horizontal plane;

a third set of bond pads located on the top surface of the horizontal package section and electrically connected to the second set of bond pads and to the second conductive layers; and

a set of connectors located on the bottom surface off the horizontal package section and electrically connected to the second conductive layers.

26. The electronic system as claimed in claim 25, further comprising:

one or more discrete capacitors electrically connected to one or more of the multiple second conductive layers.

17. A method for fabricating an electronic circuit package, the method comprising:

fabricating a vertical package section, which includes multiple first conductive layers separated by multiple first dielectric layers, wherein the multiple first conductive layers and the multiple first dielectric layers are oriented in parallel with a vertical plane, and wherein a top surface and a bottom surface of the vertical package section are parallel with a horizontal plane that is perpendicular to the vertical plane;

forming a first set of bond pads on the top surface of the vertical package section and electrically connected to the multiple first conductive layers; and

forming a second set of bond pads on the bottom surface of the vertical package section and electrically connected to the multiple first conductive layers.

23. An electronic system comprising:

an integrated circuit package that includes

a vertical package section having multiple first conductive layers separated by multiple first dielectric layers, wherein the multiple first conductive layers and the multiple first dielectric layers are oriented in parallel with a vertical plane, and wherein a top surface and a bottom surface of the vertical package section are parallel with a horizontal plane that is perpendicular to the vertical plane,

a first set of bond pads located on the top surface of the vertical package section and electrically connected to the multiple first conductive layers, and

a second set of bond pads located on the bottom surface of the vertical package section and electrically connected to the multiple first conductive layers; and

one or more integrated circuits located on the top surface of the vertical package section and electrically connected to the first set of bond pads.