Radio-frequency communication apparatus and associated methods

• US 20030003887A1
• Filed: 02/13/2002
• Published: 01/02/2003
• Est. Priority Date: 05/29/1998
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Lim, Lysander, Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Wang, Caiyi, Welland, David R., Kerth, Donald A., Srinivasan, Vishnu S.
• Application Number:
  US10/075,094
• Publication Number:
  US 20030003887A1
• Time in Patent Office: Days
• US Class Current: 455/147
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A voltage-controlled oscillator (VCO) generates an output signal with adjustable frequency. The VCO circuitry includes a variable capacitor circuitry and a voltage-generator circuitry. In response to a plurality of control signals, the variable capacitor circuitry adjusts the frequency of an output signal of the VCO circuitry. The voltage-generator circuitry generates the plurality of control signals and provides them to the variable capacitor circuitry. The voltage level of each of the plurality of the control signals differs by an offset voltage from the voltage level of the remaining signals in the plurality of signals.

Claims

1. A voltage-controlled oscillator circuitry, comprising:

a variable capacitor circuitry, the variable capacitor circuitry configured to adjust the frequency of an output signal of the voltage-controlled oscillator circuitry in response to a plurality of control signals; and

a control circuitry, the control circuitry configured to generate the plurality of control signals in response to an input control signal,

wherein the voltage level of each of the plurality of the control signals differs by an offset voltage from the voltage level of the remaining signals in the plurality of signals.

2. A radio-frequency (RF) apparatus, comprising:

a first circuit partition, comprising receiver analog circuitry configured to produce a digital receive signal from an analog radio-frequency signal; and

a second circuit partition, comprising receiver digital circuitry configured to accept the digital receive signal, wherein the first and second circuit partitions are partitioned so that interference effects between the first circuit partition and the second circuit partition tend to be reduced.