Pulse signal circuit, parallel processing circuit, pattern recognition system, and image input system

• US 20030004907A1
• Filed: 05/28/2002
• Published: 01/02/2003
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Matsugu, Masakazu
• Granted Patent: US 7,085,749 B2
• Time in Patent Office: Days
• US Class Current: 706/26
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06V 10/454 Integrating the filters into a hierarchical structure, e.g. convolutional neural networks [CNN]
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding

Abstract

A synaptic connection element for connecting neuron elements inputs a plurality of pulsed signals from different neuron elements N1 through N4, effects a common modulation (time window integration or pulse phase/width modulation) on a plurality of predetermined signals among the plurality of pulse signals, and outputs the modulated pulse signals to different signal lines to a neuron element M1. A neural network for representing and processing pattern information by the pulse modulation is thereby downsized in scale.

Claims

1. A pulse signal processing circuit comprising:

a modulation circuit for inputting a plurality of pulsed signals from different arithmetic elements and modulating in common a plurality of predetermined signals among the plurality of pulse signals, wherein the modulated pulse signals are outputted in branch to different signal lines, respectively.

2. A pulse signal processing circuit according to claim 1, wherein said modulation circuit is a delay circuit for giving a predetermined delay to the pulse signal.

3. A pulse signal processing circuit according to claim 1, wherein said modulation circuit gives a time-differing modulation characteristic with respect to a process of the same input data.

4. A parallel processing circuit comprising:

a plurality of neuron elements; and

synaptic connection elements for connecting said neuron elements,

wherein said parallel processing circuit is constructed by use of said pulse signal processing circuit claimed in claim 1.

5. A parallel processing circuit according to claim 4, wherein said synaptic connection element shares a plurality of synaptic connections as one circuit on the basis of a distribution symmetry of synaptic connections to said predetermined neuron elements.

6. A pattern recognition system comprising:

data input means for inputting data of a predetermined dimension;

a plurality of data processing modules having feature detection layers for detecting a plurality of features; and

output means for outputting a result of a pattern recognition,

wherein said data processing module includes a plurality of arithmetic elements connected to each other by predetermined synaptic connection means, each of said arithmetic element outputs a pulsed signal at a frequency or timing corresponding to an arrival time patter of a plurality of pulses within a predetermined time window,

said output means outputs, based on the outputs of said plurality of arithmetic elements, a result of detecting or recognizing a predetermined pattern, and said synaptic connection means includes a modulation circuit for inputting the plurality of pulsed signals from said different arithmetic elements and effecting a predetermined common modulation on a plurality of predetermined pulsed signals among the plurality of pulsed signals, and outputs in branch the modulated pulse signals to different signal lines.

7. A pattern recognition system according to claim 6, wherein said modulation circuit is a delay circuit for giving a predetermined delay to the pulse signal.

8. A pattern recognition system according to claim 6, wherein said modulation circuit gives a time-differing modulation characteristic with respect to a process of the same input data.

9. A pattern recognition system according to claim 6, wherein said modulation circuit is a pulse width modulation circuit for effecting a predetermined pulse width modulation on the pulse signal.

10. A pulse signal processing circuit comprising:

a modulation circuit for inputting a plurality of pulsed signals from different arithmetic elements and giving a predetermined delay to each pulse; and

a branch circuit for outputting in branch the modulated pulse signals in a predetermined sequence to different signal lines respectively in a way that gives a predetermined delay to the pulse signal.

11. A pattern recognition system according to claim 10, wherein said modulation circuit gives a time-differing modulation characteristic with respect to a process of the same input data.

13. A parallel processing circuit according to claim 12, wherein said synaptic connection element includes a modulation circuit for inputting the plurality of pulsed signals from said different arithmetic elements and effecting a predetermined common modulation on each pulse, and outputs in branch the modulated pulse signals to different signal lines.

15. A pulse signal processing circuit according to claim 14, wherein said parallel modulation circuit is a pulse width modulation circuit for effecting a predetermined pulse width modulation on the pulse signal.

16. A pulse signal processing circuit according to claim 14, wherein outputs of said arithmetic elements are, after being stored in a predetermine d memory, outputted in branch to other arithmetic elements.

17. A pulse signal processing circuit according to claim 14, wherein said time window integration circuit multiplies the pulse signal by a predetermined weighting coefficient set for every pulse signal inputted in parallel to said parallel modulation circuit and configuring a receptive field of said arithmetic element.

18. A pulse signal processing circuit according to claim 14, further comprising a weighting coefficient signal generation circuit, wherein said time window integration circuit multiplies the input pulse signal by a weighting coefficient signal transmitted from said weighting coefficient signal generation circuit.

19. An image input system executing a predetermined image input by use of said pulse signal processing circuit claimed in claim 14.

12. A parallel processing circuit comprising:

a plurality of arithmetic elements, arrayed in parallel, for extracting a different feature pattern category in every predetermined area with respect to a predetermined sampling position on input data of a predetermined dimension,

wherein each of said arithmetic elements is connected to other predetermined arithmetic element through synaptic connection means, and

said plurality of arithmetic elements for extracting the different feature pattern category relative to the predetermined position on the input data, are disposed adjacent to each other.

14. A pulse signal processing circuit comprising:

a parallel modulation circuit for inputting a plurality of pulsed signals from different arithmetic elements and effecting a predetermined modulation in parallel on a plurality of predetermined signals among the plurality of pulse signals; and

integration means for integrating outputs of said parallel modulation circuit,

wherein said parallel modulation circuit includes a plurality of time window integration circuits for effecting a predetermined weighted time window integration with respect to a plurality of predetermined signals among the modulated pulse signals, and

said arithmetic element outputs a predetermined pulse signal on the basis of a signal from said integration means.

20. A pulse signal processing circuit comprising:

a timing signal generation circuit;

a plurality of arithmetic elements for outputting pulse signals; and

connection means for connecting said arithmetic elements,

wherein said connection means inputs the pulse signals from said predetermined arithmetic elements and executes a predetermined weighted time window integration, and

said arithmetic elements are disposed in parallel by said connection means and integrate the pulse modulation signals from said connection means on the basis of a timing signal from said timing signal generation circuit.

21. An image input system executing a predetermined image input by use of said pulse signal processing circuit claimed in claim 20.