Hardware emulation of parallel ATA drives with serial ATA interface
First Claim
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1. An apparatus comprising:
- an access detector to detect an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, the access being intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels;
a mapping circuit to map the serial ports to the parallel channels; and
a state machine coupled to the access detector and the mapping circuit to emulate a response from the one of the parallel channels based on the access type and the mapped serial ports.
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Abstract
An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.
71 Citations
51 Claims
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1. An apparatus comprising:
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an access detector to detect an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, the access being intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels;
a mapping circuit to map the serial ports to the parallel channels; and
a state machine coupled to the access detector and the mapping circuit to emulate a response from the one of the parallel channels based on the access type and the mapped serial ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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18. A method comprising:
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detecting an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, the access being intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels;
mapping the serial ports to the parallel channels; and
emulating a response from the one of the parallel channels based on the access type and the mapped serial ports by a state machine.
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35. A system comprising:
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a plurality of serial storage devices; and
a chipset coupled to the serial storage devices, the chipset having a serial storage controller, the serial storage controller comprising;
an access detector to detect an access type of an access to one of a plurality of serial ports interfacing to the serial storage devices, the access being intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels, a mapping circuit to map the serial ports to the parallel channels, and a state machine coupled to the access detector and the mapping circuit to emulate a response from the one of the parallel channels based on the access type and the mapped serial ports.
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Specification