Microprocessor configuration with encryption
First Claim
Patent Images
1. A microprocessor configuration, comprising:
- a central processing unit;
a functional unit;
a memory unit;
each of said central processing unit, said memory unit, and said functional unit having a first encryption unit with;
a first means for providing an alterable key; and
a first combinational logic element;
said memory unit having a second encryption unit with;
a second means for providing a key; and
a second combinational logic element;
a bus;
said first encryption unit connecting said central processing unit to said bus;
said second encryption unit connecting said functional unit to said bus;
said third encryption unit connecting said memory unit to said bus;
said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging data therebetween; and
said second combinational logic element connected between said first alterable key providing means and said first combinational logic element.
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Abstract
A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.
43 Citations
32 Claims
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1. A microprocessor configuration, comprising:
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a central processing unit;
a functional unit;
a memory unit;
each of said central processing unit, said memory unit, and said functional unit having a first encryption unit with;
a first means for providing an alterable key; and
a first combinational logic element;
said memory unit having a second encryption unit with;
a second means for providing a key; and
a second combinational logic element;
a bus;
said first encryption unit connecting said central processing unit to said bus;
said second encryption unit connecting said functional unit to said bus;
said third encryption unit connecting said memory unit to said bus;
said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging data therebetween; and
said second combinational logic element connected between said first alterable key providing means and said first combinational logic element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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17. A microprocessor configuration, comprising:
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a central processing unit;
a functional unit;
a memory unit;
each of said central processing unit, said memory unit, and said functional unit having a first encryption unit with;
an alterable key providing device; and
a first combinational logic element;
said memory unit having a second encryption unit with;
a key providing device; and
a second combinational logic element;
a bus;
said first encryption unit connecting said central processing unit to said bus;
said second encryption unit connecting said functional unit to said bus;
said third encryption unit connecting said memory unit to said bus;
said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging data therebetween; and
said second combinational logic element connected between said alterable key providing device and said first combinational logic element.
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Specification