Methods and apparatus for storing memory test information

• US 20030005353A1
• Filed: 05/31/2002
• Published: 01/02/2003
• Est. Priority Date: 06/08/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology America Incorporated (Renesas Electronics Corporation)
• Inventors: Mullins, Michael A., Sauvageau, Anthony J.
• Granted Patent: US 7,178,072 B2
• Time in Patent Office: Days
• US Class Current: 714/5
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Methods and apparatus for storing memory test information are presented. The method includes the steps of storing a portion of information related to locations and numbers of failed memory cells detected while testing memory, and updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable. The first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

Claims

1. A method for storing memory test information, the method comprising the steps of:

storing a portion of information related to locations and numbers of failed memory cells detected while testing memory; and

updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable;

wherein the first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

2. The method of claim 1, wherein the stored information is updated to indicate the type of memory spare to be assigned to repair the failed memory cell based in part on whether a number of failed memory cells in a respective row or column portion of memory where the failed memory cell is located exceeds a number of available complementary type memory spares.

3. The method of claim 2, wherein the information is stored in a table having row and column portions, each row and column portion of the table including at least one address/error-count entry pair for storing an address of the respective row or column portion of memory where the failed memory cell is located and the number of failed memory cells detected in the respective row or column portion of memory.

4. The method of claim 3, further comprising the step of:

determining if a match exists between at least one of the addresses of the row and column portions of memory where the failed memory cell is located and an address entry stored in the table.

5. The method of claim 4, wherein if a match exists, the method further comprises the step of:

incrementing the error-count entry paired with the matching address entry if the paired error-count entry is equal to the number of available complementary type memory spares.

6. The method of claim 4, wherein if a match exists in both the row and column portions of the table, the method further comprises the step of:

incrementing the error-count entries paired with the matching address entries if the paired error-count entries are each less than the respective number of available complementary type memory spares.

7. The method of claim 4, wherein if a match exists in one of the row and column portions of the table, the method further comprises the step of:

determining if the row or column portion of the table not including the matching address entry is full.

8. The method of claim 7, wherein if the row or column portion of the table not including the matching address entry is not full, the method further comprises the steps of:

incrementing the error-count entry paired with the matching address entry if the paired error-count entry is less than the number of available complementary type memory spares; and

adding an address/error-count entry pair to the portion of the table not including the matching address entry, the added entry pair including the address of the row or column portion of memory where the failed memory cell is located not matching an address entry in the table and an error-count of one.

9. The method of claim 7, wherein if the row or column portion of the table not including the matching address entry is full, the information stored in the table is updated to indicate that the memory is not repairable.

10. The method of claim 4, wherein if no match exists, the method further comprises the step of:

determining if at least one of the row and column portions of the table are full.

11. The method of claim 10, wherein if neither of the row or column portions of the table are full, the method further comprises the step of:

adding an address/error-count entry pair to both the row and column portions of the table, each added entry pair including the respective address of the row or column portion of memory where the failed memory cell is located and an error-count of one.

12. The method of claim 10, wherein if at least one of the row and column portions of the table are full, the information stored in the table is updated to indicate that the memory is not repairable.

13. The method of claim 4, wherein if a total number of one type of memory spare is greater than a total number of complementary type memory spares, the step of determining if a match exists comprises the step of:

comparing the address of the row or column portion of memory corresponding to the type of memory spare having the greater total number of spares with address entries in the table before comparing the address of the row or column portion of memory corresponding to the type of memory spare having a lesser total number of spares with address entries in the table.

14. The method of claim 4, wherein if the total number of the first and second types of memory spares are equal, the step of determining if a match exists comprises the steps of:

selecting one of the addresses of the row and column portions of memory where the failed memory cell is located at random; and

comparing the address of the row or column portion of memory selected at random with address entries in the table before comparing the address of the row or column portion of memory not selected at random with address entries in the table.

15. The method of claim 3, further comprising the step of:

linking address/error-count entry pairs included in the row portion of the table with associated address/error-count entry pairs included in the column portion of the table.

16. The method of claim 15, wherein a link identifier entry for storing a unique link ID is added to each address/error-count pair of the row or column portion of the table corresponding to the type of memory spare having a greater total number of spares for linking address/error-count entry pairs included in the row portion of the table with associated address/error-count entry pairs included in the column portion of the table.

17. The method of claim 16, wherein the number of unique link IDs is equal to the number of memory spares of the type having a lesser total number of spares.

18. The method of claim 3, wherein the table represents a portion of memory where at least one of the first type of memory spare intersects at least one of the second complementary type of memory spare.

19. The method of claim 3, wherein the size of the table is determined by the equation:

20. The method of claim 1, wherein the row portion of memory includes at least one row of memory and the column portion of memory includes at least one column of memory.

21. The method of claim 1, wherein the column portion of memory includes at least one input/output (I/O) device, the at least one I/O device providing an input and output path for at least one column of memory.

22. An apparatus for storing memory test information, comprising:

logic that stores a portion of information related to locations and numbers of failed memory cells detected while testing memory; and

logic that updates the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable;

wherein the first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

23. The apparatus of claim 22, wherein the stored information is updated to indicate the type of memory spare to be assigned to repair the failed memory cell based in part on whether a number of failed memory cells in a respective row or column portion of memory where the failed memory cell is located exceeds a number of available complementary type memory spares.

24. The apparatus of claim 23, further comprising:

a table for storing the information, the table having row and column portions, each row and column portion of the table including at least one address/error-count entry pair for storing an address of the respective row or column portion of memory where the failed memory cell is located and the number of failed memory cells detected in the respective row or column portion of memory.

25. The apparatus of claim 24, further comprising:

logic that determines if a match exists between at least one of the addresses of the row and column portions of memory where the failed memory cell is located and an address entry stored in the table.

26. The apparatus of claim 25, further comprising:

logic that increments the error-count entry paired with the matching address entry when a match exists if the paired error-count entry is equal to the number of available complementary type memory spares.

27. The apparatus of claim 25, further comprising:

logic that increments the error-count entries paired with the matching address entries when a match exists in both the row and column portions of the table if the paired error-count entries are each less than the respective number of available complementary type memory spares.

28. The apparatus of claim 25, further comprising:

logic that determines if the row or column portion of the table not including the matching address entry is full when a match exists in one of the row and column portions of the table.

29. The apparatus of claim 28, further comprising:

logic that increments the error-count entry paired with the matching address entry when a match exists in one of the row and column portions of the table if the paired error-count entry is less than the number of available complementary type memory spares; and

logic that adds an address/error-count entry pair to the portion of the table not including the matching address entry when a match exists in one of the row and column portions of the table, the added entry pair including the address of the row or column portion of memory where the failed memory cell is located not matching an address entry in the table and an error-count of one.

30. The apparatus of claim 28, further comprising:

logic that indicates that the memory is not repairable when the row or column portion of the table not including the matching address entry is full.

31. The apparatus of claim 25, further comprising:

logic that determines if at least one of the row and column portions of the table are full when no match exists.

32. The apparatus of claim 31, further comprising:

logic that adds an address/error-count entry pair to both the row and column portions of the table when no match exists, each added entry pair including the respective address of the row or column portion of memory where the failed memory cell is located and an error-count of one.

33. The apparatus of claim 31, further comprising:

logic that indicates that the memory is not repairable when at least one of the row and column portions of the table are full.

34. The apparatus of claim 25, wherein the logic that determines if a match exists comprises:

logic that compares the address of the row or column portion of memory corresponding to the type of memory spare having the greater total number of spares with address entries in the table before comparing the address of the row or column portion of memory corresponding to the type of memory spare having a lesser total number of spares with address entries in the table when a total number of one type of memory spare is greater than a total number of complementary type memory spares.

35. The apparatus of claim 25, wherein the logic that determines if a match exists comprises:

logic that selects one of the addresses of the row and column portions of memory where the failed memory cell is located at random when the total number of the first and second types of memory spares are equal; and

logic that compares the address of the row or column portion of memory selected at random with address entries in the table before comparing the address of the row or column portion of memory not selected at random with address entries in the table when the total number of the first and second types of memory spares are equal.

36. The apparatus of claim 24, further comprising:

logic that links address/error-count entry pairs included in the row portion of the table with associated address/error-count entry pairs included in the column portion of the table.

37. The apparatus of claim 36, further comprising:

logic that adds a link identifier entry for storing a unique link ID to each address/error-count pair of the row or column portion of the table corresponding to the type of memory spare having a greater total number of spares for linking address/error-count entry pairs included in the row portion of the table with associated address/error-count entry pairs included in the column portion of the table.

38. The apparatus of claim 37, wherein the number of unique link IDs is equal to the number of memory spares of the type having a lesser total number of spares.

39. The apparatus of claim 24, wherein the table represents a portion of memory where at least one of the first type of memory spare intersects at least one of the second complementary type of memory spare.