Testing architecture for a semiconductor memory device

• US 20030005372A1
• Filed: 06/28/2001
• Published: 01/02/2003
• Est. Priority Date: 06/28/2001
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Hsiao, K. T., Yang, Li-Yang, Lo, Hao-Liang
• Granted Patent: US 6,986,082 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A testing architecture for a semiconductor memory device is described. The testing architecture comprises a microprocessor, as well as a result sorting and display device. When a start signal is received by the microprocessor, a clock signal is output from the microprocessor to the semiconductor memory device so that a data storing signal is output from the memory device to the microprocessor. When the data storing signal is received by the microprocessor, the data storing signal is tested and compared, and a testing result signal is output. The resorting and display device is used to output the start signal to the microprocessor, receive the result signal, and sort the result signal so as to display whether data stored by the semiconductor memory device is correct.

Claims

1. A testing architecture for a semiconductor memory device, used for testing the semiconductor memory device, the testing architecture comprising:

a microprocessor, wherein when a start signal is received by the microprocessor, a clock signal is output from the microprocessor and transmitted to the semiconductor memory device so that a data storing signal is output from the semiconductor memory device to the microprocessor, wherein when the data storing signal is received by the microprocessor, the data storing signal is tested, compared, and a testing result signal is output; and

a result sorting and display, used to output the start signal to the microprocessor, receive the result signal, and sort the result signal so as to display whether data stored by the semiconductor memory device is correct.

2. The testing architecture of the semiconductor memory device according to claim 1, wherein the microprocessor has a function of receiving serial data, and testing and comparing the data.

3. The testing architecture for the semiconductor memory device according to claim 2, wherein the microprocessor comprises an 8051 integrated circuit (IC).

4. A testing architecture for a semiconductor memory device, used for testing the semiconductor memory device, the testing architecture comprising:

a microprocessor, wherein when a start signal is received by the microprocessor, a clock signal is output from the microprocessor and transmitted to the semiconductor memory device so as to output a data storing signal in series from the semiconductor memory device to the microprocessor, wherein when the data storing signal is received in series by the microprocessor, the data storing signal is tested, compared, and a testing result is output through a result signal; and

a result sorting and display device, used to output the start signal to the microprocessor, receive the result signal, and sort the result signal so as to display if data stored by the semiconductor memory device is correct.

5. The testing architecture of the semiconductor memory device according to claim 4, wherein the microprocessor comprises an 8051 integrated circuit (IC).