Method and apparatus for testing multi-core processors

• US 20030005380A1
• Filed: 06/29/2001
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Miner, David E., Nguyen, Hang T.
• Application Number:
  US09/895,695
• Publication Number:
  US 20030005380A1
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

An apparatus and method for testing multi-core processors by simultaneously testing each of the multiple cores. The full vector of test results for a master core is sent to the test equipment for evaluation while the test results for the slave(s) are logically compared to those of the master, with the result of the comparison reduced to one or more bits.

Claims

1. An apparatus for testing multi-core processors, comprising:

a test input connector electrically coupled to a master processor and a slave processor for simultaneously providing a test signal to said master and said slave processors;

a test output connector electrically coupled to said master processor for monitoring a master processor test result; and

a comparator electrically coupled to said master processor and said slave processor for comparing said master processor test result and a slave processor test result and storing a match result.

2. An apparatus in accordance with claim 1, wherein:

said comparator uses a single bit for comparing said master processor test result and said slave processor test result.

3. An apparatus in accordance with claim 1, further comprising:

a multi-core test reporter coupled to said test output connector and coupled to said comparator for reporting a result of said master processor test result and said match result.

4. An apparatus in accordance with claim 1, wherein:

said master processor and said slave processor are present on a single die.

6. An apparatus in accordance with claim 1, wherein:

said comparator uses one bit for comparing each of said plurality of slave processors to said master processor.

7. An apparatus in accordance with claim 1, wherein:

said master processor and said plurality of slave processors are present on a single die.

8. An apparatus in accordance with claim 1, further comprising:

a multi-core test reporter coupled to said test output connector and coupled to said comparator for reporting a result of said master test result and said match result.

5. An apparatus for testing multi-core processors, comprising:

a test input connector electrically coupled to a master processor and a plurality of slave processors simultaneously providing a test signal to said master and said slave processors;

a test output connector electrically coupled to said master processor for monitoring a master processor test result;

a comparator electrically coupled to said master processor and said plurality of slave processors for comparing said master processor test result and a plurality of slave processor test result and storing a match result.

9. An apparatus for testing multi-core processors with internal core checking logic, comprising:

a test input connector electrically coupled to a master processor and a slave processor for simultaneously providing a test signal to said master and said slave processors;

a test output connector electrically coupled to said master processor for monitoring a master test result;

a core checking logic driver for controlling the internal core checking logic and reporting a deviation between said master and said slave in response to said test signal.

10. An apparatus in accordance with claim 9, wherein:

said master processor and said slave processor are present on a single die.

11. An apparatus in accordance with claim 9, further comprising:

a multi-core test reporter coupled to said test output connector and coupled to said core checking logic driver for reporting a result of said master test result and said deviation.

13. A method in accordance with claim 12, further comprising:

repeating said functional test on said second processor when said first processor fails said functional test.

14. A method in accordance with claim 12, wherein:

creating said first match result uses a single bit accumulate register.

15. A method of testing in accordance with claim 12, wherein:

said comparing of functional test results is performed on the multi-core processor.

16. A method of testing in accordance with claim 12, wherein:

said comparing of functional test results is performed externally to the multi-core processor.

17. A method of testing in accordance with claim 12, wherein:

creating said first match result is performed on the multi-core processor.

18. A method of testing in accordance with claim 12, wherein:

creating said first match result is performed externally to the multi-core processor.

19. A method of testing in accordance with claim 12, further comprising:

comparing said functional test results on said first processor with said functional test results on a third processor;

creating a second match result and;

reporting said second match result.

12. A method for testing multi-core processors, comprising:

running a functional test on each of a plurality of processors simultaneously;

monitoring said functional test results on a first processor;

comparing said functional test results on said first processor with said functional test results on a second processor and creating a first match result and;

reporting said functional test results on said first processor and said first match result.

20. A multi-core processor testing system, comprising:

supplying a test instruction set to the multi-core processor for execution on a plurality of cores;

receiving a test vector representing the execution of said test instructions by a first core;

comparing the execution of said test instruction by a second core with said test vector;

creating a slave condition bit from said comparing step.

21. A system in accordance with claim 20, further comprising:

reporting a quality condition status for the multi-core processor.