Semiconductor device and method of manufacturing the same

• US 20030006444A1
• Filed: 06/05/2002
• Published: 01/09/2003
• Est. Priority Date: 07/06/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kimura, Masatoshi, Amo, Atsushi
• Granted Patent: US 6,690,053 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11 and silicide layer 15 of gate wiring 6, W plug 26 electrically connecting doped polysilicon 18 and a first layer aluminum wiring, and W plug 25 electrically connecting the silicide layer over the surface of diffused layer 11 in the logic SRAM region and the first layer aluminum wiring.

Claims

1. A semiconductor device in which DRAMs and SRAMs are combined, said device comprising in the SRAM region:

a first silicide layer formed on the surface of a diffused layer adjacent to a gate electrode;

a second silicide layer on the surface of said gate electrode;

an insulating side wall formed over the sidewall of said gate electrode;

a first contact hole opened in a first interlayer dielectric formed on top, and exposing said side wall and said first and second silicide layers in the hole;

a first contact which constitutes a shared contact between said first and second silicide layers through a first plug within said first contact hole;

a second contact hole opened in a second interlayer dielectric formed on top;

a first wiring layer formed on this second interlayer dielectric;

a second contact for connecting electrically said first contact to said first wiring layer through a second plug within said second contact hole;

a third contact hole opened in said first and second interlayer dielectrics, and exposing said first silicide layer on the surface of said diffused layer in the hole; and

a third contact for connecting electrically said first silicide layer to said first wiring layer through said second plug within said third contact hole.

2. The semiconductor device according to claim 1, wherein the third contact formed in the third contact hole has the first plug between the second plug and the first silicide on the surface of the diffused layer.

3. The semiconductor device according to claim 1, further comprising in the DRAM region:

an insulating side wall over the sidewall of a gate electrode;

a lower contact formed through the first plug within the first contact hole which is opened in the first interlayer dielectric formed on top, adjacent to said gate electrode, and exposes the surface of the diffused layer; and

an upper contact formed through the second plug within the second contact hole opened in the second interlayer dielectric formed on top, and connecting electrically the lower contact to the first wiring layer.

4. The semiconductor device according to claim 3, wherein the first contact is formed in the same process as the lower contact of the DRAM.

5. The semiconductor device according to claim 3, wherein the second and third contacts are formed in the same process as the upper contact of the DRAM.

6. The semiconductor device according to claim 1, wherein at least one of the first and second plugs is made of a metal containing tungsten.

7. The semiconductor device according to claim 2, wherein the second interlayer dielectric is constituted by stacking a second dielectric on a first dielectric, and the second contact hole is opened by selective etching between said first and second dielectrics.

8. The semiconductor device according to claim 7, wherein the first and second dielectrics are respectively constituted by silicon nitride and silicon oxide.

9. A method of manufacturing a semiconductor device in which DRAMs and SRAMs are combined, comprising the steps of:

forming a insulating side wall over the sidewall of a gate electrode;

converting the surface of a diffused layer and the surface of the gate electrode into silicide;

forming a first interlayer dielectric;

forming the opening of a lower contact of the DRAM and the opening of a first contact of the SRAM in the first interlayer dielectric;

forming first plugs within the opening of the lower contact of the DRAM and the opening of the first contact of the SRAM;

forming a dielectric for selective-etching over the DRAM;

forming a capacitor layer over the DRAM while forming a second interlayer dielectric over the SRAM;

forming the opening of an upper contact of the DRAM, the opening of a second contact of the SRAM, and the opening of a third contact of the SRAM; and

forming second plugs within the opening of the upper contact of the DRAM, the opening of the second contact of the SRAM, and the opening of the third contact of the SRAM.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the first plug is formed in the opening of the lower contact of the DRAM, and in a region which constitutes a shared contact among the openings of the first contact of the SRAM.