Trench structure for semiconductor devices

• US 20030006452A1
• Filed: 07/03/2001
• Published: 01/09/2003
• Est. Priority Date: 07/03/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok
• Granted Patent: US 6,683,363 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOS trench structure integrated with a semiconductor device, for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate; a plurality of in-line trenches formed in the semiconductor substrate, a peripheral trench separated from and at least partially surrounding the in-line trenches, a dielectric material lining the trenches; and a conductive material substantially filling the dielectric-lined trenches.

Claims

1. A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, said MOS trench structure comprising:

a semiconductor substrate;

a plurality of in-line trenches formed in the semiconductor substrate, each in-line trench defined by ends, sidewalls and a bottom, and each two adjacent in-line trenches separated by mesas containing the semiconductor device, said mesas having a mesa width; and

a peripheral trench defined by ends, sidewalls and a bottom said peripheral trench at least partially surrounding the in-line trenches, said peripheral trench being spaced from the ends of the in-line trenches by an in-line trench to peripheral trench spacing;

a dielectric material lining the in-line and peripheral trenches; and

a conductive material substantially filling the dielectric-lined trenches.

2. The MOS trench structure according to claim 1, wherein the in-line trench to peripheral trench spacing is approximately equal to one-half the mesa width.

3. The MOS trench structure according to claim 1, wherein the semiconductor substrate comprises:

a semiconductor contact layer within which the trenches are formed; and

an epitaxially-grown semiconductor layer formed on a first major surface of the contact layer, said epitaxially-grown semiconductor layer having a doping concentration that is lower than a doping concentration of the contact layer.

4. The MOS trench structure according to claim 3, further comprising:

a first metal contact layer formed on an opposing second major surface of the semiconductor contact layer.

5. The MOS structure according to claim 4, wherein the semiconductor device, further comprises a second metal layer formed over the mesas and the dielectric-lined, conductive-material-filled, in-line and peripheral trenches.

6. A MOS trench structure integrated with a Schottky barrier rectifier for enhancing the breakdown characteristics of the semiconductor device, said MOS trench structure, comprising:

a semiconductor contact layer; and

an epitaxially-grown semiconductor layer formed on a first major surface of the contact layer, said epitaxially-grown semiconductor layer having a doping concentration that is lower than a doping concentration of the contact layer;

a first metal contact layer formed on an opposing and second major surface of the semiconductor contact layer;

a plurality of in-line trenches formed in the epitaxially-grown semiconductor layer, each trench defined by ends, sidewalls and a bottom and each two adjacent in-line trenches separated by mesas having a mesa width; and

a peripheral trench defined by ends, sidewalls and a bottom, said peripheral trench at least partially surrounding the in-line trenches, and said peripheral trench being spaced from the ends of the in-line trenches by an in-line trench to peripheral trench spacing;

a dielectric material lining the in-line and peripheral trenches;

a conductive material substantially filling the dielectric-lined trenches; and

a second metal contact layer covering the mesas and the conductive-material-filled trenches in-line and peripheral trenches.

7. The structure according to claim 6, wherein the first and second metal contact layers comprise the cathode and anode contacts for the Schottky barrier rectifier.

8. The structure according to claim 6, wherein the in-line trench to peripheral trench spacing is approximately equal to one-half the mesa width.

9. A MOS trench structure integrated with a radio frequency field effect transistor (RF FET) for enhancing the breakdown characteristics of the RF FET, said MOS trench structure, comprising:

a semiconductor contact layer having a first conductivity type; and

an epitaxially-grown semiconductor layer formed on a first surface of the semiconductor contact layer, said epitaxially-grown semiconductor layer having the same conductivity type as the epitaxially-grown semiconductor layer but with a higher doping concentration;

a first metal contact layer formed on an opposing and second major surface of the semiconductor contact layer;

a plurality of in-line trenches formed in the epitaxially-grown semiconductor layer, each trench defined by ends, sidewalls and a bottom and each two adjacent in-line trenches separated by mesas having a mesa width; and

a peripheral trench defined by ends, sidewalls and a bottom, said peripheral trench at least partially surrounding the in-line trenches, and said peripheral trench being spaced from the ends of the in-line trenches by an in-line trench to peripheral trench spacing;

a dielectric material lining the in-line and peripheral trenches; and

a conductive material substantially filling the dielectric-lined trenches.

10. The structure according to claim 9, wherein the RF FET comprises:

well regions of a second conductivity type formed in upper corners of the mesas, each two well regions in a mesa separated by a gap;

source regions of the first conductivity type formed in the well regions; and

gate regions formed over portions of the source regions and a portion of the gap within each mesa.

11. The structure according to claim 9, wherein the in-line trench to peripheral trench spacing is approximately equal to one-half the mesa width.

12. A MOS trench structure integrated with a semiconductor device, for enhancing the breakdown characteristics of the semiconductor device, comprising:

a semiconductor substrate;

a plurality of in-line trenches formed in the semiconductor substrate,

a peripheral trench separated from and at least partially surrounding the in-line trenches,

a dielectric material lining bottoms and sidewalls of the trenches; and

a conductive material substantially filling the dielectric-lined trenches.