Power MOSFET having enhanced breakdown voltage

• US 20030006453A1
• Filed: 06/04/2002
• Published: 01/09/2003
• Est. Priority Date: 06/05/2001
• Status: Active Grant

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Yang, Xin, Samudra, Ganesh Shankar, Liang, Yung Chii, Gan, Kian Paau
• Granted Patent: US 6,853,033 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/31675 of silicon
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET includes a dielectric, preferably in the form of a metal thick oxide that extends alongside the MOSFET'"'"'s drift region. A voltage across this dielectric between its opposing sides exerts an electric field into the drift region to modulate the drift region electric field distribution so as to increase the breakdown voltage of a reverse biased semiconductor junction between the drift region and body region. This allows for higher doping of the drift region, for a given breakdown voltage when compared to conventional MOSFETs.

Claims

1. A power metal oxide semiconductor field effect transistor (MOSFET), comprising:

a source region;

a drain region;

a gate;

a body region;

a drift region extending between said body region and drain region, to at least partially guide current from said drain region to said source region;

a dielectric having opposing sides, one of its opposing sides extending alongside said drift region, and an opposite one of its opposing sides connected to a conducting region, so that a voltage across said dielectric between its opposing sides exerts an electric field into said drift region to redistribute free carriers in said drift region and thereby affect the electrical field distribution in said drift region to increase the breakdown voltage of a reverse biased semiconductor junction between said drift region and said body region.

2. The MOSFET of claim 1, further comprising another dielectric having opposing sides, one of its opposing sides extending alongside a second side of said drift region, and an opposite one of its opposing sides connected to a conducting region, so that a voltage across said dielectric between its opposing sides exerts an electric field into said drift region to redistribute free carriers in said drift region and thereby affect the electrical field distribution in said drift region to increase the breakdown voltage of a reverse biased semiconductor junction between said drift region and said body region.

3. The MOSFET of claim 1, wherein said dielectric comprises a metal oxide insulator.

4. The MOSFET of claim 3, wherein said metal oxide insulator comprises a single or multi layer oxide insulator.

5. The MOSFET of claim 3, wherein said dielectric is formed having a thickness t_ox, so that the relationship N_d≈

[(ε

_si·

E₀²·

ε

_ox^4/3)/(2·

q^7/3)]^3/7·

[t_ox·

w ]<sup>−

4/7</sup> is satisfied, where N_d is the concentration of dopant in said drift region, 2w is a thickness of said drift region, ε

_ox is the dielectric constant for said dielectric, ε

_si is the dielectric constant for said drift region, E₀ is the electric field avalanche value for said drift region and q is the electron charge.

6. The MOSFET of claim 5, wherein a ratio of said thickness of said dielectric and a thickness of said conducting region connected to one of its opposite side, to a half width of said drift region is approximately 4:

3.

7. The MOSFET of claim 1, further comprising an electrical contact, electrically connecting said source region and said conducting region.

8. The MOSFET of claim 1, further comprising:

an electrical contact, electrically connected to said source region and isolated from said conducting region and said dielectric;

a second electrical contact electrically interconnected with said conducting region to allow application of a control voltage to control a voltage across said dielectric and thereby influence said breakdown voltage of said reverse biased semiconductor junction between said drift region and said body region.

9. The MOSFET of claim 1, wherein said conducting region comprises a poly-silicon layer along an extent of said opposite one of said opposing sides of said dielectric.

10. The MOSFET of claim 1, wherein said semiconductor wafer is formed of silicon.

11. The MOSFET of claim 1, wherein said conductive region comprises a polysilicon.

12. The MOSFET of claim 1, wherein said semiconductor wafer is formed of n type silicon.

14. The method of claim 13, wherein said defined thickness of said dielectric is t_ox, and t_ox is chosen so that the relationship N_d≈

[(ε

_si·

E₀²·

ε

_ox^4/3)/(2·

q^7/3)]^3/7·

[t_ox·

w]<sup>−

4/7</sup> is satisfied, where N_d is the concentration of dopant in said drift region, 2w is a the distance between vertical extending trenches, ε

_ox is the dielectric constant for said dielectric, ε

_Si is the dielectric constant for said drift region, E₀ is the electric field avalanche value for said drift region, and q is the electron charge.

15. The method of claim 13, wherein said covering is formed by wet oxidation.

16. The method of claim 13, wherein said conductive material comprises a polysilicon.

17. The method of claim 16, wherein said wafer is formed of silicon.

18. The method of claim 16, wherein said polysilicon comprises POCI₃ doped silicon.

19. The method of claim 13, wherein each of said trenches are formed by forming and combining a plurality of proximate trenches thinner than said each of said opposed vertical trenches.

20. The method of claim 13, wherein said double diffused MOSFET structure comprises a planar gate.

21. The method of claim 13, wherein said double diffused MOSFET structure comprises a trenched gate.

22. The method of claim 13, further comprising doping said region between said trenches with desired impurities using a tilted implantation process.

24. The MOSFET of claim 23, wherein said drift region extends vertically between said source region and said drain region.

25. The MOSFET of claim 23, wherein said drift region extends laterally between said source region and said drain region.

13. A method of forming a metal oxide semiconductor transistor (MOSFET) in a semiconductor wafer comprising:

forming opposed vertically extending trenches in said semiconductor wafer;

covering interior walls of each of said trenches with a dielectric material of a defined thickness;

filling a volume of each of said trenches between said dielectric material with a conductive material;

forming a double diffused MOSFET structure between said opposed vertical trenches, said MOSFET structure formed to have a drift region that abuts said dielectric material along at least a portion of its vertical extent.

23. A n-channel or p-channel power metal oxide semiconductor field effect transistor (MOSFET), comprising:

a source region;

a drain region;

a gate;

a body region;

a drift region extending between said body region and drain region, to at least partially guide current from said source region to said drain region;

two dielectric columns each having opposing sides, one opposing side of each of said two dielectric columns extending alongside said drift region, and an opposite one of said opposing sides of each of said dielectric columns electrically connected to a conducting region, so that a voltage across each of said two dielectric columns between its opposing sides exerts an electric field into said drift region to redistribute free carriers in said drift region and thereby affect the electrical field distribution in said drift region to increase the breakdown voltage of a reverse biased semiconductor junction between said drift region and said body region.