Semiconductor device and manufacturing method thereof

• US 20030006456A1
• Filed: 08/20/2002
• Published: 01/09/2003
• Est. Priority Date: 07/19/1995
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Tetsuo, Nakamura, Katsumi, Minato, Tadaharu, Harada, Masana
• Granted Patent: US 6,867,437 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A pin diode is formed by a p⁺ collector region, an n type buffer region, an n⁻ region and an n⁺ cathode region. A trench is formed from the surface of n⁺ cathode region through n⁺ cathode region to reach n⁻ region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n⁺ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n⁺ cathode region. An anode electrode is formed to be electrically connected to p⁺ collector region. The n⁺ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Claims

1. A semiconductor device including a diode structure in which main current flows between first and second main surfaces sandwiching an intrinsic or a first conductivity type semiconductor substrate, comprising:

A first impurity region of a first conductivity type formed at said first main surface of said semiconductor substrate and having a higher impurity concentration than that of said semiconductor substrate;

a second impurity region of a second conductivity type formed at said second main surface of said semiconductor substrate, sandwiching with said first impurity region, a low impurity concentration region of said semiconductor substrate;

wherein

said semiconductor substrate has a plurality of trenches extending parallel to each other at said first main surface, each said trench being formed to reach said low impurity concentration region of said semiconductor substrate from said first main surface through said first impurity region, and

said first impurity region is formed entirely at said first main surface of said semiconductor substrate between said trenches extending parallell to each other;

said device further comprising;

a control electrode layer formed in said trench to be opposed to said first impurity region and said low impurity concentration region of said semiconductor substrate with an insulating film interposed;

a first electrode layer formed on said first main surface of said semiconductor substrate and electrically connected to said first impurity region; and

a second electrode layer formed on said second main surface of said semiconductor substrate and electrically connected to said second impurity region.

2. The semiconductor device according to claim 1, wherein

said plurality of trenches includes first, second and third trenches extending parallel to each other;

said first impurity region being formed entirely at said first main surface of said semiconductor substrate between said first and second trenches;

a third impurity region of the second conductivity type is formed at said first main surface of said semiconductor substrate between said second and third trenches; and

said third impurity region being made shallower than said trench and electrically connected to said first electrode layer.

3. The semiconductor device according to claim 1, further comprising

an isolation impurity region of the second conductivity type formed at said first main surface of said semiconductor substrate, wherein

at one side of outermost one of said plurality of trenches extending parallel to each other, another one of said trenches is positioned, and at the other side, said isolation impurity region is formed in contact with the outermost trench and deeper than said trench, said isolated impurity region is not directly connected to said first electrode layer.

4. The semiconductor device according to claim 1, wherein

depth of said trench from said first main surface is from 5 μ

m to 15 μ

m.

5. A semiconductor device including a pnpn structure in which main current flows between first and second main surfaces sandwiching an intrinsic or a first conductivity type semiconductor substrate, comprising:

a first impurity region of a first conductivity type formed at said first main surface of said semiconductor substrate;

a second impurity region of a second conductivity type formed at said second main surface of said semiconductor substrate; and

a third impurity region of the second conductivity type formed below said first impurity region and sandwiching, with said second impurity region, a region of said semiconductor substrate;

wherein

said semiconductor substrate has a plurality of trenches extending parallel to each other at said first main surface, each said trench being formed to reach said region of said semiconductor substrate from said first main surface through said first and third impurity regions,

said first impurity region being formed entirely over said first main surface of said semiconductor substrate between said trenches extending parallel to each other;

said device further comprising;

a control electrode layer formed in said trench to oppose to said region of said semiconductor substrate and said first and third impurity regions with an insulating film interposed;

a first electrode layer formed on said first main surface of said semiconductor substrate and electrically connected to said first impurity region; and

a second electrode layer formed on said second main surface of said semiconductor substrate and electrically connected to said second impurity region.

6. The semiconductor device according to claim 5, wherein

said plurality of trenches includes first, second and third trenches extending parallel to each other;

said first impurity region being formed entirely at said first main surface of said semiconductor substrate between said first and second trenches,

a fourth impurity region of the second conductivity type is formed at said first main surface of said semiconductor substrate between said second and third trenches, and

said fourth impurity region being made shallower than said trench and electrically connected to said first electrode layer.

7. The semiconductor device according to claim 5 further comprising

an isolation impurity region of the second conductivity type formed at said first main surface of said semiconductor substrate, wherein

at one side of outermost one of said plurality of trenches extending parallel to each other, another one of said trenches is positioned, and at the other side, said isolation impurity region is formed in contact with the outermost trench and deeper than said trench, said isolated impurity region is not directly connected to said first electrode layer.

8. The semiconductor device according to claim 5 wherein

depth of said trench from said first main surface is from 5 μ

m to 15 μ

m.

9. A semiconductor device including a diode structure in which main current flows between first and second main surfaces sandwiching an intrinsic or a first conductivity type semiconductor substrate, comprising:

a first impurity region of a first conductivity type formed at said first main surface of said semiconductor substrate and having a higher impurity concentration than that of said semiconductor substrate; and

a second impurity region of a second conductivity type formed at said second main surface of said semiconductor substrate;

wherein

said semiconductor substrate has trenches extending parallel to each other formed at said first main surface to sandwich said first impurity region;

said device further comprising;

a third impurity region of the second conductivity type formed on a sidewall of the trench at said first main surface to be adjacent to said first impurity region;

a forth impurity region of the first conductivity type having lower concentration than said first impurity region, formed immediately below said third impurity regions to be in contact with the sidewall of said trench and the region of said semiconductor substrate and to be adjacent to said first impurity region;

a control electrode layer formed in said trench to oppose to said region of said semiconductor substrate and said third and fourth impurity regions with an insulating film interposed;

a first electrode layer formed on said first main surface of said semiconductor substrate and electrically connected to said first and third impurity regions; and

a second electrode layer formed at said second main surface of said semiconductor substrate and electrically connected to said second impurity region.

10. The semiconductor device according to claim 9, further comprising

an isolation impurity region of the second conductivity type formed at said first main surface of said semiconductor substrate, wherein

at one side of outermost one of said plurality of trenches extending parallel to each other, another one of said trenches is positioned, and at the other side, said isolation impurity region is formed in contact with the outermost trench and deeper than said trench, said isolated impurity region is not directly connected to said first electrode layer.

11. The semiconductor device according to claim 9, wherein

depth of said trench from said first main surface is from 5 μ

m to 15 μ

m.

13. The semiconductor device according to claim 12, wherein

depth of said trench from said first main surface is 5 μ

m to 15 μ

m.

14. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second and third trenches;

said first, third and fourth impurity regions are formed at said semiconductor substrate between said first and second trenches;

only said low concentration region of said semiconductor substrate is positioned at said first main surface of said semiconductor substrate between said second and third trenches;

a conductive layer is formed on said semiconductor substrate between said second and third trenches with a second insulating film interposed; and

said conductive layer is electrically connected to each of said control electrode layers filling said second and third trenches.

15. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second and third trenches;

said first, third and fourth impurity regions are formed at said semiconductor substrate between said first and second trenches;

a fifth impurity region of the second conductivity type is formed at said first main surface of said semiconductor substrate between said second and third trenches;

a conductive layer is formed on said semiconductor substrate between said second and third trenched with a second insulating film interposed; and

said conductive layer is electrically connected to each said control electrode layer filling said second and third trenches.

16. The semiconductor device according to claim 12, further comprising a fifth impurity region of a second conductivity type having a lower concentration than said first impurity region, formed below said first impurity region to be in contact with a sidewall of said trench, and to sandwich with said second impurity region said low concentration region of said semiconductor substrate.

17. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second, third and fourth trenches;

said first and second trenches are arranged adjacent to each other, a region of said semiconductor substrate between said first and second trenches is a first region where said first, third and fourth impurity region are formed;

said third and fourth trenches are arranged adjacent to each other, a region of said semiconductor substrate between said third and fourth trenches is a second region where said low concentration region of said semiconductor substrate only is positioned at said first main surface;

a plurality of said second regions are arranged between two said first regions;

a conductive layer is formed at said first main surface with a second insulating film interposed, in said plurality of said second regions between said first regions; and

said conductive layer is electrically connected to each said control electrode layer filling said third and fourth trenches sandwiching each of said second regions.

18. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second, third, forth, fifth and sixth trenches;

said first and second trenches are arranged adjacent to each other, the region of said semiconductor substrate between said first and second trenches is a first region where said first, third and fourth impurity regions are formed;

said third and fourth trenches are arranged adjacent to each other, the region of said semiconductor substrate between said third and fourth trenches is a second region where said low concentration region of said semiconductor substrate only is positioned at said first main surface;

said fifth and sixth trenches are arranged adjacent to each other, the region of said semiconductor substrate between said fifth and sixth trenches is a third region where a fifth impurity region of the second conductivity type is formed at said first main surface;

a plurality of said second regions are arranged between said first and third regions;

said first electrode layer is electrically connected to said fifth impurity region;

a conductive layer is formed on said first main surface with said second insulating film interposed in said plurality of said second regions between said first and third regions; and

said conductive layer is electrically connected to each said control electrode layer filling said third and fourth trenches sandwiching each of said second regions.

19. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second, third and fourth trenches;

said first and second trenches are arranged adjacent to each other, the region of said semiconductor substrate between said first and second trenches is a first region where said first, third and fourth impurity regions are formed;

said third and fourth trenches are arranged adjacent to each other, the region of said semiconductor substrate between said third and fourth trenches is a second region where said low concentration region of said semiconductor substrate only is positioned at said first main surface;

a plurality of said second regions are arranged between two said first regions;

said first electrode layer is formed on said first main surface with only a second insulating film interposed, in said plurality of second regions between first regions; and

said control electrode layer protrudes upward from said first main surface.

20. The semiconductor device according to claim 12, wherein

said trench includes a plurality of trenches including first, second, third, fourth, fifth and sixth trenches;

said first and second trenches are arranged adjacent to each other, the region of the semiconductor substrate between said first and second trenches is a first region where said first, third and fourth impurity regions are formed;

said third and fourth trenches are arranged adjacent to each other, the regions of said semiconductor substrate between said third and fourth trenches is a second regions where said low concentration region of said semiconductor substrate only is formed at said first main surface;

said fifth and sixth trenches are arranged adjacent to each other, the regions of said semiconductor substrate between said fifth and sixth trenches is a third region where a fifth impurity region of the second conductivity type is formed at said first main surface;

a plurality of said second regions are arranged between said first and third regions;

said first electrode layer is electrically connected to said fifth impurity region;

in said plurality of second regions between said first and third regions, said first electrode layer is formed on said first main surface with only a second insulating film interposed; and

said control electrode layer protrudes upward from said first main surface.

12. A semiconductor device in which current flows between first and second main surfaces of an intrinsic or a first conductivity type semiconductor substrate, comprising:

a first impurity region of a second conductivity type formed at said first main surface side of said semiconductor substrate; and

a second impurity region of the second conductivity type formed at said second main surface of said semiconductor substrate and sandwiching, with said first impurity region, a low concentration region of said semiconductor substrate;

wherein

said semiconductor substrate has a trench reaching said low concentration region of said semiconductor substrate from said first main surface through said first impurity region;

said device further comprising;

a third impurity region of a first conductivity type formed on said first impurity region to be in contact with a sidewall of said trench at said first main surface of said semiconductor substrate;

a fourth impurity region of the second conductivity type having a higher concentration than said first impurity region formed on said first impurity region to be adjacent to said third impurity region at said first main surface of said semiconductor substrate;

a control electrode layer formed in said trench to oppose to said first and third impurity regions and said low concentration region of said semiconductor substrate with an insulating film interposed, for controlling current flowing between said first and second main surfaces by an applied control voltage;

a first electrode layer formed at said first main surface of said semiconductor substrate and electrically connected to said third and fourth impurity regions; and

a second electrode layer formed at said second main surface of said semiconductor substrate and electrically connected to said second impurity region;

wherein

when said first and second main surfaces of said semiconductor substrate are conducted, an accumulation region of the first conductivity type is formed along the periphery of said trench and in contact with said third impurity region, and a ratio Rn=n/(n+p) of contact area n of an effective cathode region including said third impurity region and said accumulation region with said first impurity region and said low concentration region of said semiconductor substrate with respect to contact area p of said first impurity region with said low concentration region of said semiconductor substrate is, in said conducted state, 0.4 to 1.0.

21. A semiconductor device in which current flows between first and second main surfaces of an intrinsic or a first conductivity type semiconductor substrate, comprising:

a first impurity region of a second conductivity type formed on said first main surface side of said semiconductor substrate; and

a second impurity region of the second conductivity type formed on said second main surface of said semiconductor substrate, sandwiching, with said first impurity region, a low concentration region of said semiconductor substrate;

wherein

said semiconductor substrate includes a trench reaching said low concentration region of said semiconductor substrate from said first main surface through said first impurity region;

said device further comprising;

a third impurity region of the first conductivity type on said first impurity region to be in contact with a sidewall of said trench at said first main surface of said semiconductor substrate;

a fourth impurity region of the second conductivity type having a higher concentration than said first impurity region, formed on said first impurity region and adjacent to said third impurity region at said first main surface of said semiconductor substrate;

a control electrode layer formed in said trench to oppose to said first and third impurity regions and said low concentration region of said semiconductor substrate with an insulating film interposed, for controlling current flowing between said first and second main surfaces by an applied control voltage;

a first electrode layer formed on said first main surface of said semiconductor substrate and electrically connected to said third and fourth impurity regions; and

a second electrode layer formed on said second main surface of said semiconductor substrate and electrically connected to said second impurity region;

wherein

the following expression is satisfied where Dt represents depth of said trench from said first main surface, Wt represents width of said trench, De represents depth of said third impurity region from said first main surface, We represents width of said third impurity region from one of said trenches to another of said trenches, and Pt represents pitch of adjacent said trenches;

$\frac{2<br><br>\left(W<br><br>\text{\hspace{1em}<br><br>}<br><br>e+D<br><br>\text{\hspace{1em}<br><br>}<br><br>t-D<br><br>\text{\hspace{1em}<br><br>}<br><br>e\right)+W<br><br>\text{\hspace{1em}<br><br>}<br><br>t}{2<br><br>\left(W<br><br>\text{\hspace{1em}<br><br>}<br><br>e+D<br><br>\text{\hspace{1em}<br><br>}<br><br>t-D<br><br>\text{\hspace{1em}<br><br>}<br><br>e\right)+P<br><br>\text{\hspace{1em}<br><br>}<br><br>t}\ge <br><br>0.4.$

22. A method of manufacturing a semiconductor device in which current flows between first and second main surfaces of an intrinsic or a first conductivity type semiconductor substrate, comprising the steps of:

forming a first impurity region of a second conductivity type by performing selective ion implantation on said first main surface of the semiconductor device of the first conductivity type;

forming a second impurity region of the second conductivity type at said second main surface of said semiconductor substrate;

forming a third impurity region of the first conductivity type at said first main surface in said first impurity region by selective ion implantation;

forming a plurality of trenches including a first, second and third trenches in said semiconductor substrate by performing anisotropic etching on said first main surface;

wherein

the first and third impurity regions are positioned at said first main surface between said first and second trenches, and only a low impurity concentration region of said semiconductor substrate is positioned at said first main surface between said second and third trenches;

said method further comprising the steps of;

forming a control electrode layer in said trench to oppose to the low concentration region of said semiconductor substrate sandwiched between said first and second impurity regions and to said first and third impurity regions, with an insulating film interposed;

forming a fourth impurity region of the second conductivity type having higher impurity concentration than said first impurity region at said first main surface in said first impurity region to be adjacent to said third impurity region by selective ion implantation;

forming a first electrode layer on said first main surface to be electrically connected to said third and fourth impurity regions; and

forming a second electrode layer on said second main surface to be electrically connected to said second impurity region.

23. The method of manufacturing a semiconductor device according to claim 22, further comprising the step of, after formation of said trench, oxidizing an inner wall of said trench to forme an oxide film and removing said oxide film.

24. The method of manufacturing a semiconductor device according to claim 22, wherein

said step of forming said control electrode layer includes the steps of:

forming a conductive film on said first main surface to fill said trenches; and

patterning said conductive film to leave the conductive film in said trench, removing said conductive film on said first main surface between said first and second trenches, and leaving said conductive film on said first main surface between said second and third trenches with a second insulating film interposed.

25. The method of manufacturing a semiconductor device according to claim 22, wherein

said step of forming said control electrode layer includes the steps of:

forming a conductive film on said first main surface to fill said trenches; and

patterning said conductive film to remove said conductive film on said first main surface between said first and second trenches and on said first main surface between said second and third trenches to fill said trenches, and to form a control electrode layer protruding upward from said first main surface.