Hermetically sealed microstructure package

• US 20030006502A1
• Filed: 06/05/2002
• Published: 01/09/2003
• Est. Priority Date: 04/10/2000
• Status: Active Grant

• Current Assignee: Maurice Karpman
• Original Assignee: Maurice Karpman
• Inventors: Karpman, Maurice
• Granted Patent: US 6,828,674 B2
• Time in Patent Office: Days
• US Class Current: 257/711
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00357 involving bonding one or several substrates on a non-temporary support, e.g. another substrate
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Claims

1. A process for manufacturing microstructure packages, the process comprising the following steps:

sealing a plurality of microstructures on a surface of a sheet, each within an individual cavity;

providing electrical connections to the individual microstructures;

providing a protectant for the electrical connections while the surface is intact; and

dividing the sheet into individual microstructure assemblies.

2. The process of claim 1 wherein the step of providing electrical connections includes electrically connecting the surface to an upper portion of the seal of the microstructure.

3. The process of claim 1 wherein the step of sealing includes the following steps:

surrounding the microstructure with a coolable material;

attaching an upper surface to the coolable material; and

allowing the material to cool thereby forming a sealed cavity containing the microstructure.

4. The process of claim 3 wherein the upper surface is a prefabricated wafer.

5. The process of claim 3 wherein the upper surface is a wafer with an attached flex circuit.

6. The process of claim 1 wherein the step of dividing consists of separating the microstructure assemblies by using a wafer saw.

7. The process of claim 1 wherein the step of providing electrical connections consists of using a wire bond to electrically connect the microstructure surface to the upper level of the seal.

8. The process of claim 1 wherein the step of providing a protectant consists of pouring an overmold between the microstructure cavities.

9. A process for manufacturing wafer-scale microstructure packages, the process comprising the following steps:

sealing a plurality of microstructures on a surface of a sheet while the surface is intact; and

separating the surface of a sheet into individual microstructure packages.

10. The process of claim 9 wherein the step of sealing consists of sealing microstructures within a cavity so that the microstructures are free to move while at the same time protecting electrical connectors to the microstructure while keeping the entire package chip-sized.

11. A chip-sized microstructure package comprising:

a microstructure sealed within a cavity;

an electrical connection element electrically connecting the microstructure to an exterior of the cavity; and

a protective layer covering the electrical connection.

12. A chip-sized microstructure package according to claim 11 wherein the microstructure is sealed within a cavity by a material surrounding the microstructure and an upper surface adhered to the surrounding material.

13. A chip-sized microstructure package according to claim 12 wherein the surrounding material is frit glass.

14. A chip-sized microstructure package according to claim 12, wherein the upper surface is a preprinted cap wafer.

15. A chip-sized microstructure package according to claim 12, wherein the electrical connection from the microstructure to the exterior of the cavity is a wire bond which connects a wafer substrate to a cap surface.

16. A chip-sized microstructure package according to claim 12, wherein the protective layer is an overmold.