Semiconductor device, method of measuring the same, and method of manufacturing the same

• US 20030006795A1
• Filed: 01/22/2002
• Published: 01/09/2003
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Mitsui, Yasuhiro, Kamohara, Shiro, Ohji, Yuzuru, Arakawa, Fumiko, Asayama, Kyoichiro
• Granted Patent: US 6,881,597 B2
• Time in Patent Office: Days
• US Class Current: 324/763
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.

Claims

1. A semiconductor device,

wherein a plurality of TEGs comprising rectangular first electrode pads having a side length of 0.5 μ

m or shorter and constituted of an uppermost layer wiring are arranged in a scribe region.

2. A semiconductor device,

wherein a plurality of TEGs comprising rectangular first electrode pads having a side length of 1 μ

m or shorter and constituted of an uppermost layer wiring are arranged in a scribe region.

3. A semiconductor device,

wherein a plurality of TEGs comprising rectangular first electrode pads having a side length of 10 μ

m or shorter and constituted of an uppermost layer wiring are arranged in a scribe region.

5. The semiconductor device according to claim 3,

wherein a plurality of TEGs comprising rectangular second electrode pads having a side length of 20 μ

m or longer and constituted of said uppermost layer wiring are further arranged in the scribe region.

6. The semiconductor device according to claim 3,

wherein a length of one side of said first electrode pad is not longer than the dimension obtained by adding a diameter of a connection hole between said first electrode pad and a lower layer wiring thereof and the length of an alignment margin between said first electrode pad and said connection hole.

7. The semiconductor device according to claim 3,

wherein a length of one side of said first electrode pad is about four-thirds of a diameter of a connection hole between said first electrode pad and a lower layer wiring thereof.

8. The semiconductor device according to claim 3,

wherein said scribe region is covered with a protection film.

9. The semiconductor device according to claim 3,

wherein said first electrode pad is exposed in an island shape.

10. The semiconductor device according to claim 5,

wherein a surface of said first electrode pad is covered with a protection film and a surface of said second electrode pad is partially exposed by removing said protection film.

12. The semiconductor device according to claim 5,

wherein said second electrode pad is connected commonly to a plurality of the TEGs.

4. A semiconductor device,

wherein a plurality of TEGs are arranged in a scribe region, said plurality of ETGs comprising rectangular first electrode pads having a side length of 10 μ

m or shorter and constituted of an uppermost layer wiring; and

rectangular second electrode pads having a side length of 20 μ

m or longer and constituted of said uppermost layer wiring.

11. The semiconductor device according to claim 4,

wherein said second electrode pad is connected commonly to a plurality of the TEGs.

15. The method of measuring a semiconductor device according to claim 14,

wherein an improvement of a yield of the semiconductor device is achieved.

16. The method of measuring a semiconductor device according to claim 14,

wherein said protection film on said first electrode pad is removed by a focused ion beam method or a selective etching method.

17. The method of measuring a semiconductor device according to claim 14,

wherein a plurality of TEGs comprising rectangular second electrode pads having a side length of 20 μ

m or longer and constituted of said uppermost layer wiring, are further arranged in a second scribe region while a surface of said second electrode pad is partially exposed by removing said protection film on said second electrode pad.

19. The method of measuring a semiconductor device according to claim 18,

wherein an improvement of a yield of the semiconductor device is achieved.

20. The method of measuring a semiconductor device according to claim 18,

wherein the predetermined part of said protection film is removed by a focused ion beam method or a selective etching method.

21. The method of measuring a semiconductor device according to claim 18,

wherein said logic circuit comprises n input terminals and m output terminals, and n+m+3 probes are contacted to said extraction electrodes to evaluate a logic value of said logic circuit.

22. The method of measuring a semiconductor device according to claim 21,

wherein one of said probes is a probe for contact confirmation.

24. The method of measuring a semiconductor device according to claim 23,

wherein an improvement of a yield of the semiconductor device is achieved.

25. The method of measuring a semiconductor device according to claim 23,

wherein a predetermined part of said protection film is removed by a focused ion beam method or a selective etching method.

27. The method of manufacturing a semiconductor device according to claim 26,

wherein said step (a) includes the step of forming second electrode pads having a side length of 20 μ

m or longer and constituted of said uppermost layer wiring in said scribe region, and said step (c) includes the step of partially exposing a surface of said second electrode pad.

29. The method of manufacturing a semiconductor device according to claim 28,

wherein said step (c) includes the step of forming in a product circuit region a bonding pad formed together with a connection member, said step (d) includes the step of forming a protection film on an upper layer of said bonding pad, and said step (e) includes the step of partially exposing a surface of said bonding pad by removing a predetermined part of said protection film in said product circuit region.

30. The method of manufacturing a semiconductor device according to claim 28,

wherein said step (c) includes the step of forming in a second scribe region a second electrode pad formed together with a connection member, and forming in a product circuit region a bonding pad formed together with a connection member, said step (d) includes the step of forming a protection film on an upper layer of said second electrode pad and said bonding pad, and said step (e) includes the step of removing a predetermined part of said protection film in said second scribe region, thereby partially exposing a surface of said second electrode pad, and removing a predetermined part of said protection film in said product circuit region, thereby partially exposing a surface of said bonding pad.

13. A semiconductor device,

wherein a plurality of TEGs comprising an extraction electrode constituted of an uppermost layer wiring are arranged in a product circuit region.

14. A method of measuring a semiconductor device,

wherein a plurality of TEGs comprising rectangular first electrode pads having a side length of 10 μ

m or shorter and constituted of an uppermost layer wiring, are arranged in a first scribe region while a surface of said first electrode pad is covered with a protection film, and

after partially exposing the surface of said first electrode pad by removing said protection film on said first electrode pad, a probe having a tip radius of curvature of about 0.05 μ

m to 0.8 μ

m is contacted to said first electrode pad, and then said TEG is measured.

18. A method of measuring a semiconductor device,

wherein a logic circuit is arranged in a product circuit region whose uppermost layer is covered with a protection film, and

after exposing a part of a surface of an extraction electrode constituted of an uppermost layer wiring by removing a predetermined part of said protection film, a probe having a tip radius of curvature of about 0.05 μ

m to 0.8 μ

m is contacted to said extraction electrode to evaluate a logic value of said logic circuit.

23. A method of measuring a semiconductor device,

wherein a TEG is arranged in a product circuit region whose uppermost layer is covered with a protection film, and

after exposing a part of a surface of an extraction electrode constituted of an uppermost layer wiring by removing a predetermined part of said protection film, a probe having a tip radius of curvature of about 0.05 μ

m to 0.8 μ

m is contacted to said extraction electrode to evaluate said TEG.

26. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming rectangular first electrode pads in a scribe region, said pads having a side length of 10 μ

m or shorter and constituted of an uppermost layer wiring and forming a bonding pad constituted of said uppermost layer wiring in a product circuit region;

(b) forming a protection film on an upper layer of said uppermost layer wiring; and

(c) partially exposing a surface of said bonding pad by removing a predetermined part of said protection film,

wherein said uppermost layer wiring is formed by depositing a conductive body and the patterning by the lithography method.

28. A method of manufacturing a semiconductor device, comprising the steps of:

(a) sequentially forming a first insulating film, a stopper insulating film, and a second insulating film on a semiconductor substrate;

(b) forming a connection hole in said first insulating film and forming a wiring trench in said stopper insulating film and said second insulating film;

(c) burying a conductor film in said connection hole and said wiring trench, and removing said conductor film in a region outside said connection hole and said wiring trench by a CMP method, thereby forming in a first scribe region a first electrode pad formed together with a connection member;

(d) forming a protection film on an upper layer of said first electrode pad; and

(e) removing said protection film and said second insulating film in said first scribe region with said stopper insulating film used as an etching stopper layer, thereby exposing said first electrode pad.