Split cascode driver

• US 20030006842A1
• Filed: 07/03/2001
• Published: 01/09/2003
• Est. Priority Date: 07/03/2001
• Status: Abandoned Application

• Current Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Turudic, Andy, Davenport, William H.
• Application Number:
  US09/898,602
• Publication Number:
  US 20030006842A1
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages

Abstract

Two transistors are coupled in a cascode topology between a load resistor and a first current source. A third transistor is coupled between the cascode transistor output terminal and a second current source. The current provided by the second current source causes a constant voltage drop across the load resistor and consequently a steady offset voltage at the cascode transistor output terminal. When the control transistor in the cascode circuit switches on, the current provided by the first current source provides an additional voltage drop at the cascode transistor output terminal.

Claims

1. A cascode amplifier comprising:

a first transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the first transistor is coupled to a first node;

a second transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the second transistor is coupled to the second current handling terminal of the first transistor, and wherein the second current handling terminal of the second transistor is coupled to a second node;

a third transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the third transistor is coupled to the first node;

a fourth transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the fourth transistor is coupled to the second current handling terminal of the third transistor, and wherein the second current handling terminal of the fourth transistor is coupled to a third node;

a fifth transistor comprising a control terminal and a first and a second current handling terminal, wherein the second current handling terminal of the fifth transistor is coupled to the second node;

a sixth transistor comprising a control terminal and a first and a second current handling terminal, wherein a the second current handling terminal of the sixth transistor is coupled to the third node;

a first current source coupled between the first node and a fourth node receiving a first supply voltage;

a second current source coupled between the first current handling terminal of the fifth transistor and the fourth node;

a third current source coupled between the first current handling terminal of the sixth transistor and the fourth node;

a first load resistance coupled between the second node and a fifth node receiving a second supply voltage level; and

a second load resistance coupled between the third node and the fifth node.

2. The amplifier of claim 1, wherein the control terminals of the second and fourth transistors are coupled together.

3. The amplifier of claim 1, wherein the control terminals of the fifth and sixth transistors are coupled together.

4. The amplifier of claim 1, wherein the control terminals of the second, fourth, fifth, and sixth transistors are coupled together.

5. The amplifier of claim 1, wherein the first current source is variable.

6. The amplifier of claim 1, wherein at least one of the second and third current sources is variable.

7. The amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors and the first, second, and third current sources are formed on a single integrated circuit.

8. The amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors comprise gallium arsenide.

9. The amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors comprise indium phosphide.

10. The amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors comprise silicon carbide.

11. The amplifier of claim 1, wherein the first, second, third, fourth, fifth, and sixth transistors comprise silicon-germanium.

12. The amplifier of claim 1, wherein at least one of the first, second, third, fourth, fifth, and sixth transistors is an N-type transistor, and at least one of the first, second, third, fourth, fifth, and sixth transistors is a P-type transistor.

13. The amplifier of claim 1 further comprising an electro-optical modulator coupled at the output terminal.

14. The amplifier of claim 13, wherein the modulator is an electro-absorption modulator.

15. The amplifier of claim 13, wherein the modulator is a Mach-Zehnder modulator.

16. The amplifier of claim 1 further comprising a direct modulated laser coupled at the output terminal.

18. The amplifier of claim 17, wherein the control terminals of the second and third transistors are coupled together.

19. The amplifier of claim 17, wherein the first current source is variable.

20. The amplifier of claim 17, wherein the second current source is variable.

21. The amplifier of claim 17 further comprising a load resistance coupled between the second current handling terminal of the second transistor and a node receiving a second supply voltage.

22. The amplifier of claim 17, wherein the first, second, and third transistors, and the first and second current sources, are formed on a single integrated circuit.

23. The amplifier of claim 17, wherein the first, second, and third transistors comprise gallium arsenide.

24. The amplifier of claim 17, wherein the first, second, and third transistors comprise indium phosphide.

25. The amplifier of claim 17, wherein the first, second, and third transistors comprise silicon carbide.

26. The amplifier of claim 17, wherein the first, second, and third transistors comprise silicon-germanium.

27. The amplifier of claim 17, wherein at least one of the first, second, and third transistors is an N-type transistor, and at least one of the first, second, and third transistors is a P-type transistor.

28. The amplifier of claim 17, wherein the first, second, and third transistors comprise metal oxide semiconductor field effect transistors.

29. The amplifier of claim 17 further comprising an electro-optical modulator coupled at the output terminal.

30. The amplifier of claim 29 wherein the modulator is an electro-absorption modulator.

31. The amplifier of claim 29 wherein the modulator is a Mach-Zehnder modulator.

32. The amplifier of claim 17 further comprising a direct modulated laser coupled at the output terminal.

17. A cascode amplifier comprising:

a first transistor comprising a control terminal and a first and a second current handling terminal;

a second transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the second transistor is coupled to the second current handling terminal of the first transistor;

a third transistor comprising a control terminal and a first and a second current handling terminal, wherein the second current handling terminal of the third transistor is coupled to the second current handling terminal of the second transistor;

a first current source coupled between the first current handling terminal of the first transistor and a first node receiving a supply voltage level; and

a second current source coupled between the first current handling terminal of the third transistor and the first node.

33. An electronic circuit comprising:

a first current path comprising a first current source, the first current path providing an offset voltage level at an output terminal of the circuit, the offset voltage level being offset from a supply voltage level of the circuit; and

a second current path comprising a cascode amplifier coupled to a second current source, the second current path providing a varying voltage level at the output terminal.

34. The circuit of claim 33, wherein the first current path comprises an electronic gain device and the offset voltage is a steady state voltage.

35. The circuit of claim 34, wherein the gain device comprises gallium arsenide.

36. The circuit of claim 35, wherein the gain device comprises indium phosphide.

37. The circuit of claim 35, wherein the gain device comprises silicon carbide.

38. The circuit of claim 35, wherein the gain device comprises silicon-germanium.

39. The circuit of claim 33, wherein the first current path comprises at least one N-type semiconductor gain device and at least one P-type semiconductor gain device.

40. The circuit of claim 33, wherein the cascode amplifier comprises at least two transistors coupled in a cascode topology.

41. The circuit of claim 40, wherein at least one of the transistors comprises gallium arsenide.

42. The circuit of claim 40, wherein at least one of the transistors comprises indium phosphide.

43. The circuit of claim 40, wherein at least one of the transistors comprises silicon carbide.

44. The circuit of claim 40, wherein at least one of the transistors comprises silicon-germanium.

45. The circuit of claim 33, wherein the cascode amplifier comprises at least one N-type semiconductor gain device and at least one P-type semiconductor gain device.

46. The circuit of claim 33, wherein the first current source is variable.

47. The circuit of claim 33, wherein the second current source is variable.

48. The circuit of claim 33 further comprising an electro-optical modulator coupled at the output terminal.

49. The circuit of claim 48, wherein the modulator is an electro-absorption modulator.

50. The circuit of claim 48, wherein the modulator is a Mach-Zehnder modulator.

51. The circuit of claim 33 further comprising a direct modulated laser coupled at the output terminal.

52. A method of providing a mixed output voltage signal at an output terminal of an electronic circuit, wherein the output signal comprises an offset voltage level and a varying voltage level, the offset voltage level being offset from a supply voltage level of the circuit, comprising the acts of:

passing a first current through a first current path, wherein the first current path comprises a load resistance and a first current source, and wherein the first current passing through the load resistance causes a first voltage drop across the load resistance that provides the offset voltage level; and

passing a varying current through a second current path, wherein the second current path comprises the load resistance, a cascode amplifier, and a second current source, and wherein the varying current passing through the load resistance causes a varying voltage drop across the load resistance that provides the varying voltage level.

53. The method of claim 52, wherein the method of providing the mixed output voltage signal further comprises driving an optical modulator coupled to the output terminal.

54. The method of claim 52, wherein passing the first current through the first current path comprises adjusting a current provided by the first current source to provide the offset voltage level required by a load being driven at the output terminal.

55. The method of claim 52, wherein passing the varying current through the second current path comprises receiving a varying electronic input signal at an input terminal of the cascode amplifier.

56. The method of claim 52, wherein the cascode amplifier comprises at least one transistor comprising gallium arsenide.

57. The method of claim 52, wherein the varying voltage level varies at least one volt.

58. The method of claim 52, wherein the varying voltage level varies between the offset voltage level and a predetermined modulating voltage level, and wherein the varying voltage level does not overshoot the modulating voltage level by more than approximately seven percent of the modulating voltage level as the varying voltage level switches from the offset voltage level to the modulating voltage level.