Split cascode driver
First Claim
Patent Images
1. A cascode amplifier comprising:
- a first transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the first transistor is coupled to a first node;
a second transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the second transistor is coupled to the second current handling terminal of the first transistor, and wherein the second current handling terminal of the second transistor is coupled to a second node;
a third transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the third transistor is coupled to the first node;
a fourth transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the fourth transistor is coupled to the second current handling terminal of the third transistor, and wherein the second current handling terminal of the fourth transistor is coupled to a third node;
a fifth transistor comprising a control terminal and a first and a second current handling terminal, wherein the second current handling terminal of the fifth transistor is coupled to the second node;
a sixth transistor comprising a control terminal and a first and a second current handling terminal, wherein a the second current handling terminal of the sixth transistor is coupled to the third node;
a first current source coupled between the first node and a fourth node receiving a first supply voltage;
a second current source coupled between the first current handling terminal of the fifth transistor and the fourth node;
a third current source coupled between the first current handling terminal of the sixth transistor and the fourth node;
a first load resistance coupled between the second node and a fifth node receiving a second supply voltage level; and
a second load resistance coupled between the third node and the fifth node.
1 Assignment
0 Petitions
Accused Products
Abstract
Two transistors are coupled in a cascode topology between a load resistor and a first current source. A third transistor is coupled between the cascode transistor output terminal and a second current source. The current provided by the second current source causes a constant voltage drop across the load resistor and consequently a steady offset voltage at the cascode transistor output terminal. When the control transistor in the cascode circuit switches on, the current provided by the first current source provides an additional voltage drop at the cascode transistor output terminal.
-
Citations
58 Claims
-
1. A cascode amplifier comprising:
-
a first transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the first transistor is coupled to a first node;
a second transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the second transistor is coupled to the second current handling terminal of the first transistor, and wherein the second current handling terminal of the second transistor is coupled to a second node;
a third transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the third transistor is coupled to the first node;
a fourth transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the fourth transistor is coupled to the second current handling terminal of the third transistor, and wherein the second current handling terminal of the fourth transistor is coupled to a third node;
a fifth transistor comprising a control terminal and a first and a second current handling terminal, wherein the second current handling terminal of the fifth transistor is coupled to the second node;
a sixth transistor comprising a control terminal and a first and a second current handling terminal, wherein a the second current handling terminal of the sixth transistor is coupled to the third node;
a first current source coupled between the first node and a fourth node receiving a first supply voltage;
a second current source coupled between the first current handling terminal of the fifth transistor and the fourth node;
a third current source coupled between the first current handling terminal of the sixth transistor and the fourth node;
a first load resistance coupled between the second node and a fifth node receiving a second supply voltage level; and
a second load resistance coupled between the third node and the fifth node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
17. A cascode amplifier comprising:
-
a first transistor comprising a control terminal and a first and a second current handling terminal;
a second transistor comprising a control terminal and a first and a second current handling terminal, wherein the first current handling terminal of the second transistor is coupled to the second current handling terminal of the first transistor;
a third transistor comprising a control terminal and a first and a second current handling terminal, wherein the second current handling terminal of the third transistor is coupled to the second current handling terminal of the second transistor;
a first current source coupled between the first current handling terminal of the first transistor and a first node receiving a supply voltage level; and
a second current source coupled between the first current handling terminal of the third transistor and the first node.
-
-
33. An electronic circuit comprising:
-
a first current path comprising a first current source, the first current path providing an offset voltage level at an output terminal of the circuit, the offset voltage level being offset from a supply voltage level of the circuit; and
a second current path comprising a cascode amplifier coupled to a second current source, the second current path providing a varying voltage level at the output terminal. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
-
-
52. A method of providing a mixed output voltage signal at an output terminal of an electronic circuit, wherein the output signal comprises an offset voltage level and a varying voltage level, the offset voltage level being offset from a supply voltage level of the circuit, comprising the acts of:
-
passing a first current through a first current path, wherein the first current path comprises a load resistance and a first current source, and wherein the first current passing through the load resistance causes a first voltage drop across the load resistance that provides the offset voltage level; and
passing a varying current through a second current path, wherein the second current path comprises the load resistance, a cascode amplifier, and a second current source, and wherein the varying current passing through the load resistance causes a varying voltage drop across the load resistance that provides the varying voltage level. - View Dependent Claims (53, 54, 55, 56, 57, 58)
-
Specification