Insulated gate field effect transistor and manufacturing thereof

• US 20030008462A1
• Filed: 06/07/2002
• Published: 01/09/2003
• Est. Priority Date: 06/12/2001
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Mitsuda, Katsuhiro, Ohnishi, Kazuhiro, Horiuchi, Masatada, Takahama, Takashi
• Application Number:
  US10/164,074
• Publication Number:
  US 20030008462A1
• Time in Patent Office: Days
• US Class Current: 438/282
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence

Abstract

An impurity having a high electrical activation rate is introduced into a channel region, while an In implanted layer is formed in a very shallow region of the channel region. Impurities B, P are re-distributed such that their maximum impurity concentrations are reached at the same depth of a maximum impurity concentration in the In implanted layer, to form channel impurity regions which electrically act as impurities such as B, P, with a similar depth distribution to that of In. The resulting impurity distribution contributes both to the prevention of a punch-through phenomenon and to a large current driving capability of a highly miniaturized complementary MOS transistor.

Claims

1. A method of fabricating an insulated gate field effect transistor, comprising the steps of:

implanting a first impurity from a main surface of a semiconductor substrate having a first conductive type such that said first impurity reaches a maximum impurity concentration within said semiconductor substrate; and

implanting a second impurity having the first conductive type such that a depth at which said second impurity reaches a maximum impurity concentration substantially matches with a depth at which said first impurity reaches the maximum impurity concentration.

2. A method according to claim 1, wherein said step of implanting a first impurity and said step of implanting a second impurity are reversed in order.

3. A method according to claim 1, wherein said step of implanting a first impurity includes implanting said first impurity at an angle to the main surface of said semiconductor substrate except for the perpendicular.

6. A method of manufacturing an insulated gate field effect transistor according to claim 1, wherein said first impurity is an impurity having a pinning effect on other impurities.

7. A method according to claim 6, wherein said first impurity is indium (In).

9. A method according to claim 1, wherein:

said step of implanting a second impurity having the first conductive type includes implanting said second impurity using a gate electrode as an implantation blocking mask,

wherein said method further comprising the step of;

forming a shallow source diffusion region having the second conductive type within a region in which said second impurity is implanted in said step of implanting, using the gate electrode as an implantation blocking mask.

10. A method according to claim 9, wherein said step of implanting the second impurity having the first conductive type using a gate electrode as an implantation blocking mask is performed after said step of forming a shallow source diffusion layer having the second conductive type using the gate electrode as an implantation blocking mask.

4. A method of fabricating an insulated gate field effect transistor, comprising the steps of:

forming a first conductive type region and a second conductive type region on a main surface of the same semiconductor substrate;

implanting a first impurity from the main surface of said semiconductor substrate such that said first impurity reaches a maximum impurity concentration within said semiconductor substrate;

selectively implanting a second impurity having the first conductive type into said first conductive type region such that a depth at which said second impurity reaches a maximum impurity concentration substantially matches with a depth at which said first impurity reaches the maximum impurity concentration; and

selectively implanting a third impurity having a second conductive type into said second conductive type region such that a depth at which said third impurity reaches a maximum impurity concentration matches with the depth at which said first impurity reaches the maximum impurity concentration.

5. A method according to claim 4, wherein said step of implanting a first impurity is performed after said step of implanting a second impurity and said step of implanting a third impurity.

8. A method according to claim 5, wherein said first impurity includes at least one of indium (In) and gallium (Ga).

11. A method according to claim 4, further comprising the steps of:

implanting the second impurity having the first conductive type using a gate electrode formed through a gate insulating film on a main surface of said first conductive type region as an implantation blocking mask;

forming a shallow source diffusion layer having the second conductive type within a region in which said second impurity is implanted in said step of implanting the second impurity, using the gate electrode as an implantation blocking mask;

implanting the third impurity having the second conductive type using a gate electrode formed through the gate insulating film on a main surface of said second conductive type region as an implantation blocking mask; and

forming a shallow source diffusion layer having the first conductive type within a region in which said third impurity is implanted in said step of implanting the third impurity, using the gate electrode as an implantation blocking mask.

12. A method according to claim 11, wherein said step of implanting the second impurity having the first conductive type and said step of forming a shallow source diffusion layer having the second conductive type using the gate electrode as an implantation blocking mask, and said step of implanting the third impurity having the second conductive type and said step of forming a shallow source diffusion layer having the first conductive type using the gate electrode as an implantation blocking mask are performed in a reverse order.

15. An insulated gate field effect transistor according to claim 13, wherein:

said first impurity is an impurity having an effect of pinning said second and third impurities; and

each of said second and third impurities comprises one of boron (B), phosphor (P) and arsenic (As).

16. An insulated gate field effect transistor according to claim 13, further comprising:

source diffusion layers having a relatively shallow junction depth and deep junction depth, respectively,

wherein the depth at which the maximum impurity concentration is reached in said first impurity region is at the same depth as said shallow junction depth of said source diffusion layer, or above said shallow junction depth of said source diffusion layer.

17. An insulated gate field effect transistor according to claim 13, wherein said first impurity comprises indium (In).

18. An insulated gate field effect transistor according to claim 13, wherein said first impurity comprises indium (In) or gallium (Ga).

19. An insulated gate field effect transistor according to claim 13, wherein:

each of said second and third impurity regions exhibits an impurity concentration profile which has a gradient that is more abrupt from the maximum impurity concentration point to the main surface of said semiconductor substrate than from the maximum impurity concentration point to the inside of said semiconductor substrate.

20. An insulated gate field effect transistor according to claim 13, wherein the maximum impurity concentration in each of said second and third impurity regions is 1×

10¹⁸/cm³ or higher.

21. An insulated gate field effect transistor according to claim 13, further comprising:

source diffusion layers including a shallow junction and a deep junction, respectively, wherein said second impurity region covers at least a bottom surface of said shallow junction.

22. An insulated gate field effect transistor according to claim 14, further comprising:

source diffusion layers respectively including a shallow junction and a deep junction in said first and second conductive type regions, respectively,

wherein said second impurity region or said third impurity region covers at least a bottom surface of the shallow junction of corresponding one of said source diffusion layers.

13. An insulated gate field effect transistor comprising:

a gate electrode formed on a main surface of a semiconductor substrate having a first conductive type through an insulating film;

a first impurity region formed in a region of said semiconductor substrate beneath said gate electrode; and

a second impurity region having the first conductive type formed in a region of said semiconductor substrate beneath said gate electrode,

wherein said first impurity region and said second impurity region distribute such that said first and second impurity regions have their maximum impurity concentrations at the same depth within said semiconductor substrate, and the maximum impurity concentration in said second impurity region is higher than the maximum impurity concentration in said first impurity region.

14. An insulated gate field effect transistor comprising:

a first conductive type region, and a second conductive type region having a first conductive type in a main surface region of the same semiconductor substrate;

a gate electrode formed on a main surface of each of said first and second conductive type regions through an insulating film; and

a third impurity region having a second conductive type,

wherein said first and second impurity regions distribute in said first conductive type region of said semiconductor substrate beneath said gate electrode such that said first and second impurity regions have their maximum impurity concentrations at the same depth in said semiconductor substrate;

said first and third impurity regions distribute in said second conductive type region of said semiconductor substrate beneath said gate electrode such that said first and third impurity regions distribute such that said first and third impurity regions have their maximum impurity concentrations at the same depth in said semiconductor substrate; and

the maximum impurity concentration in each of said second and third impurity regions is higher than the maximum impurity concentration in said first impurity region.