Method for making an electronic component with self-aligned drain and gate, in damascene architecture

• US 20030008496A1
• Filed: 01/31/2002
• Published: 01/09/2003
• Est. Priority Date: 06/09/2000
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Deleonibus, Simon
• Granted Patent: US 6,867,128 B2
• Time in Patent Office: Days
• US Class Current: 438/630
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention concerns a method for fabricating an electronic component with self-aligned source, drain and gate, comprising the following steps:

a) forming a dummy gate on a silicon substrate (100),

b) forming a source (118) and drain (120) either side of the dummy gate,

c) self-aligned, superficial siliciding of the source and drain,

d) depositing at least one, so-called contact, metal layer (130, 132),

e) replacing the dummy gate by at least one final gate (150).

Claims

1. Method for fabricating an electronic component with self-aligned source, drain and gate, comprising the following steps:

a) the formation of a dummy gate (112) on a silicon substrate (100), said dummy gate defining a position for a channel (121) of the component,

b) at least one implantation of doping impurities in the substrate, to form a source (118) and a drain (120) either side of the channel, using the dummy gate as implanting mask,

c) superficial, self-aligned siliciding of the source and drain,

d) depositing at least one layer of so-called contact metal (130, 132) having a total thickness greater than the height of the dummy gate, and polishing the metal layer stopping at the dummy gate,

e) replacing the dummy gate by at least one final gate (150, 160, 164) separated from the substrate by a gate insulating layer (148), and electrically insulated from the source and drain.

2. Method according to claim 1, in which step d) comprises the depositing of a first metal layer (130) and, above the first layer, a second metal layer (132) having greater mechanical resistance to polishing than the first layer, the thickness of the first metal layer being less than the height of the dummy gate, but the total thickness of the first and second layers being greater than the height of the dummy gate.

3. Method according to claim 1 also comprising, before siliciding, the formation of side spacers (114, 116) on the sides of the dummy gate.

4. Method according to claim 3, in which dual-layer spacers are formed comprising an attachment layer (114) in silicon oxide, in contact with the dummy gate, and a superficial layer (116) in silicon nitride.

5. Method according to claim 2, in which the first metal is chosen from among tungsten and titanium, and in which the second metal is chosen from among TaN, Ta and TiN.

6. Method according to claim 1 comprising, after polishing, superficial oxidation of the metal layer or layers.

7. Method according to claim 1, in which a solid substrate is used.

8. Method according to claim 1, in which a substrate of silicon on insulator type is used.

9. Method according to claim 1, in which step e) comprises the removal of the dummy gate, formation of the gate insulating layer (148), depositing at least one metal layer (150, 160, 162), so-called gate layer, having an overall thickness equal to or greater than the height of the removed dummy gate, and forming said metal layer.

10. Method according to claim 9 comprising, after the formation of the gate insulating layer (148), the depositing of a first gate metal layer (160), the depositing of at least one inter-gate dielectric layer (162), and the depositing of a second gate metal layer (164).