Digital wireless basestation

• US 20030008684A1
• Filed: 07/24/2002
• Published: 01/09/2003
• Est. Priority Date: 01/24/2000
• Status: Abandoned Application

• Current Assignee: Radioscape Limited
• Original Assignee: Radioscape Limited
• Inventors: Ferris, Gavin Robert
• Application Number:
  US10/182,043
• Publication Number:
  US 20030008684A1
• Time in Patent Office: Days
• US Class Current: 455/561
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04L 69/06 Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04W 80/00 Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: H04W 88/10 adapted for operation in multiple networks, e.g. multi-mode access points

Abstract

A digital wireless basestation is disclosed which is programmed with a hardware abstraction layer suitable for enabling one or more baseband processing algorithms to he represented using high level software. Commodity protocols and hardware turn a basestation, previously a highly expensive, vendor-locked, application specific product, into a generic, scalable baseband platform, capable of executing many different modulation standards with simply a change of software. IP is used to connect this device to the backnet, and IP is also used to feed digitised IF to and from third party RF modules, using an open data and control format.

Claims

1. A digital wireless communications basestation programmed with a virtual machine layer appropriate to baseband signal processing.

2. The basestation of claim 1 in which the virtual machine layer is suitable for enabling one or more baseband processing algorithms to be represented using high level software.

3. The basestation of claim 1 in which the virtual machine layer runs on hardware comprising a PCI-bus backplane.

4. The basestation of claim 1 in which the hardware elements within the virtual machine communicate using an open, architecture neutral messaging system.

5. The basestation of claim 4 in which I20 compliant messaging is used.

6. The basestation of claim 1 which can change from operating one set of baseband processing algorithms to another set solely through a change in software.

7. The basestation of claim 6 which can change from operating one set of baseband processing algorithms to another set solely by changes to the underlying engines, implemented in soft datapaths, or hard datapaths, or a combination of the two.

8. The basestation of claim 1 which connects to RF elements through an interface which is an open interface.

9. The basestation of claim 6 in which the open interface defines one or more of the following components:

(i) power feed;

(ii) data;

(iii) controls;

(iv) timing/synchronisation;

(v) status.

10. The basestation of claim 1 which sends an IP-based digital IF feed to a radio mast.

11. The basestation of claim 10 in which the IP feed is fed up to multiple RF units.

12. The basestation of claim 1 in which an IP feed derived from a signal received at the mast is passed down to multiple processor boards.

13. The basestation of claim 1 comprising a scheduler programmed to allow scalable processing using multiple parallel processing nodes.

14. The basestation of claim 13 in which the scheduler uses I20 based self-discovery of resources to enable it to exploit those resources in an optimal manner.

15. The basestation, of claim 13 in which the scheduler reads an ‘

a priori’

partitioning file to help shape its decisions about which datapaths ought to execute on which processing units.

16. The basestation of claim 1 operable to simultaneously run multiple standards.

17. The basestation of claim 1 in which the virtual machine layer supports underlying high MIPs algorithms common to a number of different baseband processing algorithms, and makes these accessible to high level, architecture neutral, potentially high complexity but low-MIPs control flows through a scheduler interface, which allows the control flow to specify the algorithm to be executed, together with a set of resource constraint envelopes, relating to one or more of:

time of execution, memory, interconnect bandwidth, inside of which the caller desires the execution to take place.

18. The basestation of claim 1 in which the virtual machine layer is software designed to be portable to one or more DSP architectures, one or more FPGA architectures, and/or one or more ASIC architectures.

19. The basestation of claim 1 in which the virtual machine layer is software programmed with various core processes and/or core structures and/or core functions and/or flow control and/or state management.

20. The basestation of claim 19 in which the core processes include algorithms to perform one or more of the following:

source coding, channel coding, modulation;

or their inverses, namely source decoding, channel decoding and demodulation.

21. The basestation of claim 19 or 20 in which the core structures comprise a symbol processing section (concerned with processing full symbols, regardless of whether all the information held within that symbol is to be used) and a data directed processing section, in which only those bits which hold relevant information are processed.

22. The basestton of claim 21 in which symbol rate processing comprises chip rate processing within CDMA systems.

23. The basestation of claim 21 in which the core structure is comprised of processing modules operable to allocate, share and dispose of intermediate, aligned memory buffers, and pass events between themselves.

24. The basestation of claims 19 in which the core functions include one or more of the following:

resource allocation and scheduling, including memory allocation, real time resource allocation and concurrency management.

25. The basestation of any preceding claims 19 operable to access PC debug tools.

26. The basestation of any preceding claim 19 which is operable with a component, in which only that information necessary to enable software to operate with and/or otherwise model the performance of the component is supplied by the owner of the intellectual property in the component.

27. The basestation of any preceding claim 19 which is operable with a standardised description of the characteristics (including interface and non-interface behaviour) of communications components to enable a simulator, emulator or modelling tool to accurately estimate the resource requirements of a system using those components, even when such components are distributed in a non-symmetric access architecture, and even where the pattern of use of the components can only be statistically, not deterministically modelled, due to factors such as inherent ‘

burstiness’

of the underlying data stream, or the use of multiple streams each with its own QoS and birth-death timings.

28. The basestation of claim 19 operable to model time, CPU, memory, scheduling and concurrency restraints, enabling mapping onto a real time OS, non real-time OS, virtual machine or hardware.

29. A baseband stack forming the baseband stack of a basestation as defined in any preceding claims 1-28.

30. A baseband stack as claimed in claim 29 in which real or simulated components are linked together in a pipeline using a number of standard connection types and synchronisation methods which enable the management of the pipeline to be determined by the data itself.

31. A design tool for simulating the baseband stack of claim 29 or 30, in which the design tool can link together software and hardware components using a number of standard connection types and synchronisation methods which enable the management of the pipeline to be determined by the data processed by the data flows.

32. The design tool as claimed in claim 31 in which at least some of the high level flows are specified in a procedural language such as C, C++.

33. The design tool as claimed in claim 31 in which at least some of the high level flows are specified in a state-machine language such as SDL.

36. Computer software as claimed in claim 35 in which the basestation is a basestation as claimed in claims 1-28.

38. RF elements suitable for connection to a digital radio basestation, in which the basestation is as claimed in any of claims 1-28.

34. A method of designing part or all of a digital wireless basestation device in which the step of using software programmed with a virtual machine layer appropriate to baseband signal processing.

35. Computer software suitable for a digital wireless basestation, the software operating as a hardware abstraction layer and enabling one or more baseband processing algorithms to be represented using high level software.

37. Computer hardware programmed with the computer software of claims 35-36.