Access assurance for remote memory access over network

• US 20030009432A1
• Filed: 04/19/2001
• Published: 01/09/2003
• Est. Priority Date: 04/19/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miyoshi, Takashi, Horie, Takeshi, Sugahara, Hirohide, Larson, Jeffrey D.
• Granted Patent: US 6,804,673 B2
• Time in Patent Office: Days
• US Class Current: 707/1
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: Y10S 707/99932 Access augmentation or optimizing

Abstract

A method and system provide access assurance regarding an RDMA transaction. The system comprises an initiating device and a target device placed across a network router. The initiating device and the target device are coupled to a first and a second buses, respectively. The first and the second buses are coupled to the network router through a first and a second network adaptors. The first and second network adaptors include functional units to facilitate a memory-mapped read or write on the first bus to be bridged to the second bus through the computer network. An RDMA space and an associated access assurance space are assigned to the target device in the memory space of the first bus, to which the initiating device is coupled. The initiating device may RDMA the target device by directly reading from or writing into the RDMA space assigned to the target device. To obtain access assurance information regarding the RDMA transaction, the initiator performs a read from the assurance space associated with the RDMA space of the target device in the memory space of the first bus.

Claims

1. In a computer network comprising a computer device coupled to a bus, a method for the computer device to obtain access assurance information corresponding to a direct memory access transaction sent over the computer network, the method comprising:

providing an access space for the direct memory access transaction within a memory space associated with the bus;

providing an assurance space corresponding to the access space within the memory space associated with the bus; and

reading from the assurance space to obtain the access assurance information corresponding to the direct memory access transaction.

2. The method of claim 1, wherein the access space and assurance space reside within a space for remote direct memory access in the memory space associated with the bus.

3. The method of claim 1, wherein the bus is coupled to the computer network through a network adaptor, and the access assurance information comes to the network adaptor in a response packet associated with the direct memory access transaction.

4. The method of claim 3, wherein the access assurance information is kept in the network adaptor until the computer device performs an assurance check to obtain the access assurance information.

5. The method of claim 1, wherein the direct memory access transaction is performed by accessing a target address within the access space.

6. The method of claim 5, wherein the target address includes a node identification field, an assurance field, and an address offset, and reading from the assurance space further comprises:

posting a read command on the bus with a read address including a same node identification field and a same address offset as those of the target address but a different assurance field from that of the target address.

7. A system for enabling a first device to obtain access assurance information corresponding to a direct memory access transaction targeted at a second device over a computer network, comprising:

a first PCI bus coupled to the first device; and

a first PCI network adaptor coupled between the first PCI bus and the computer network, and configured to process the direct memory access transaction and to receive from the computer network the access assurance information corresponding to the direct memory access transaction.

8. The system of claim 7, wherein the first PCI network adaptor is assigned a first address range in the PCI memory space of the first PCI bus, the second device is assigned a second address range within the first address range, and the direct memory access transaction includes a target address within the second address range.

9. The system of claim 8, wherein the first PCI network adaptor further comprises:

a PCI interface target unit coupled to the first PCI bus, and configured to recognize and receive the direct memory access transaction in response to the determination that the target address is within the second address range;

at least one buffer; and

a PCI target control unit coupled between the PCI interface target unit and the at least one buffer, and configured to form at least one block queue of data associated with the direct memory access transaction in the at least one buffer.

10. The system of claim 9, wherein the PCI target control unit comprises a first memory unit configured to store a memory location of the queued data associated with the direct memory access transaction in the at least one buffer, and a second memory unit configured to store the access assurance information corresponding to the direct memory access transaction.

11. The system of claim 10, wherein the access assurance information in the second memory unit is indexed by the memory location of the queued data associated with the direct memory access transaction.

12. The system of claim 7, further comprising:

a second PCI bus coupled to the target device; and

a second PCI network adaptor coupled between the second PCI bus and the computer network, and configured to process the direct memory access transaction, to determine the access assurance information corresponding to the direct memory access transaction, and to send the access assurance information to the first PCI network adaptor over the computer network.

13. The system of claim 12, wherein the second PCI network adaptor comprises:

a master access buffer configured to determine address information associated with the direct memory access transaction; and

a PCI interface master unit coupled between the master access buffer and the second PCI bus, and configured to translate the address information into a PCI address and to post the direct memory access transaction on the PCI bus with the PCI address.

14. The system of claim 13, wherein the PCI interface master unit determines the access assurance information for the direct memory access transaction, forms a response packet including the access assurance information, and sends the response packet to the first PCI network adaptor over the computer network according to the address information.

15. A system for enabling a first device to obtain access assurance information corresponding to a direct memory access transaction targeted at a second device over a computer network, comprising:

a bus coupled to the first device;

a network adaptor coupled to the bus for coupling the first device to the computer network, further comprising,

an interfacing means for recognizing and receiving the direct memory access transaction in response to a determination that an address associated with the direct memory access transaction is within a predetermined address range;

at least one buffer for queuing data associated with the direct memory access transaction; and

a controlling means coupled with the interfacing means for forming block queues of the data associated with the direct memory access transaction in the at least one buffer; and

a memory coupled with the controlling means, for storing access assurance information received from the computer network.

16. A system for enabling a first device to obtain access assurance information corresponding to a direct memory access transaction targeted at a second device over a computer network, comprising:

a first PCI bus coupled to the first device;

a first PCI network adaptor coupled between the first PCI bus and the computer network, and configured to process the direct memory access transaction and to receive from the computer network the access assurance information corresponding to the direct memory access transaction;

a second PCI bus coupled to a target device; and

a second PCI network adaptor coupled between the second PCI bus and the computer network, and configured to process the direct memory access transaction, to determine the access assurance information corresponding to the direct memory access transaction, and to send the access assurance information to the first PCI network adaptor over the computer network.