Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor

• US 20030009622A1
• Filed: 09/03/2002
• Published: 01/09/2003
• Est. Priority Date: 03/30/2000
• Status: Active Grant

• Current Assignee: IP-First LLC, Centaur Technology Inc (VIA Technologies)
• Original Assignee: IP-First LLC
• Inventors: Henry, G. Glenn, Hooker, Rodney E., Gaskins, Darius D.
• Granted Patent: US 7,133,968 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss, is provided. The data cache has pipeline stages that parallel portions of the main pipeline in the microprocessor. The data cache employs replay buffers to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache restores the data cache pipeline stages upon detection that stall will terminate. The data cache also detects TLB misses generated by instructions subsequent to the stalled instruction and overlaps page table walks with the stall resolution.

Claims

1. A data cache in an in-order single instruction issue microprocessor, the data cache comprising:

a cache memory, for storing data;

at least one buffer, for storing state information regarding a plurality of instructions in the data cache upon detection of a stall condition in the in-order single-issue microprocessor; and

control logic, coupled to said buffer and said cache memory, configured to detect said stall condition, to save in response thereto said state information in said buffer, and to determine during said stall condition whether data specified by one or more of said plurality of instructions is missing in said cache memory.

2. The data cache of claim 1, wherein said control logic is further configured to request said missing data from a memory coupled to the microprocessor during said stall condition.

3. The data cache of claim 2, wherein said control logic is further configured to allocate one or more response buffers in the microprocessor for receiving said requested missing data prior to requesting said missing data.

4. The data cache of claim 2, wherein said control logic is further configured to request said missing data only if said missing data is located in a non-memory-mapped I/O region of an address space of the microprocessor.

5. The data cache of claim 2, wherein said control logic is further configured to request said missing data only if said one or more of said plurality of instructions does not access an input/output address space of the microprocessor.

6. The data cache of claim 1, wherein said control logic is further configured to request a cache line including said missing data during said stall condition.

7. The data cache of claim 1, further comprising:

an address register, coupled to said cache memory, for supplying an address to said cache memory;

wherein said control logic is further configured to restore an address in said address register based on said state information stored in said buffer, wherein said control logic restores said address prior to termination of said stall condition.

8. The data cache of claim 1, wherein said stall condition is caused by an instruction in a stage of the in-order single instruction issue microprocessor in or below the data cache.

9. The data cache of claim 1, wherein said stall condition is caused by an instruction specifying data missing in said cache memory.

10. The data cache of claim 9, wherein said instruction specifying said missing data precedes said plurality of instructions.

11. The data cache of claim 1, wherein said stall condition is caused by execution of a floating-point instruction within the in-order single-issue microprocessor.

12. The data cache of claim 1, wherein said stall condition is caused by execution of an MMX instruction within the in-order single-issue microprocessor.

13. The data cache of claim 1, further comprising:

a translation lookaside buffer, configured to cache physical memory addresses translated from linear memory addresses.

14. The data cache of claim 13, wherein said stall condition is caused by said control logic detecting a physical memory address associated with an instruction preceding said plurality of instructions missing from said translation lookaside buffer.

15. The data cache of claim 1, wherein said stall condition is caused by unavailability of a store buffer in the in-order single-issue microprocessor required by a store instruction preceding said plurality of instructions.

16. The data cache of claim 1, wherein said state information comprises an address specified by one or more of said plurality of instructions for addressing said cache memory.

17. The data cache of claim 16, wherein said address is a linear memory address.

18. The data cache of claim 1, wherein said state information specifies a number of bytes of data specified by one or more of said plurality of instructions.

19. The data cache of claim 1, wherein said state information specifies an instruction type of one or more of said plurality of instructions.

20. A data cache in an in-order single instruction issue microprocessor, the data cache comprising:

a translation lookaside buffer (TLB), for storing physical memory addresses;

at least one buffer, for storing state information regarding a plurality of instructions in the data cache upon detection of a stall condition in the in-order single-issue microprocessor; and

control logic, coupled to said buffer and said TLB, configured to detect said stall condition, to save in response thereto said state information in said buffer, and to determine during said stall condition whether a physical address associated with one or more of said plurality of instructions is missing in said TLB.

21. The data cache of claim 20, wherein said control logic is further configured to perform a page table walk during said stall condition in order to translate said physical address from a virtual address specified by said one or more of said plurality of instructions.

22. A single-issue in-order pipelined microprocessor for accessing data stored in a memory coupled to the microprocessor by a bus, the microprocessor comprising:

a plurality of buffers, configured to receive data from the memory on the bus; and

a data cache, coupled to said plurality of buffers, configured to determine whether one or more instructions following a stalled instruction in the microprocessor pipeline specify data missing in the data cache;

wherein said data cache is further configured to allocate one or more of said plurality of buffers to receive said missing data and to issue one or more requests on the bus for said missing data during resolution of said stalled instruction.

23. The microprocessor of claim 22, further comprising a bus interface unit, coupled to said data cache, for interfacing with the bus.

24. The microprocessor of claim 23, wherein said bus interface unit is adapted for communication with a socket 370 bus.

25. The microprocessor of claim 23, wherein said bus interface unit is adapted for communication with a socket 7 bus.

26. The microprocessor of claim 22, further comprising:

a plurality of descriptors, coupled to said data cache, for specifying memory-mapped I/O regions of a memory address space of the microprocessor;

wherein said data cache is configured to issue said one or more requests on the bus for said missing data only if said stalled instruction does not access a memory-mapped I/O region of said memory address space.

27. The microprocessor of claim 22, further comprising:

a second plurality of buffers, coupled to said data cache, configured to provide data to the memory on the bus;

wherein said data cache is configured to determine whether said stalled instruction is stalled due to lack of availability of one of said second plurality of buffers.

29. The method of claim 28, further comprising:

issuing one or more requests on a bus coupling the microprocessor to a memory for said missing data in response to said determining.

30. The method of claim 29, further comprising:

issuing a request on said bus to said memory for data specified by said instruction prior to said issuing said one or more requests for said missing data.

31. The method of claim 28, further comprising:

receiving said data specified by said instruction from said bus prior to receiving said missing data.

32. The method of claim 31, further comprising:

allocating a buffer for receiving said data specified by said instruction prior to allocating a buffer for receiving said missing data.

33. The method of claim 28, wherein said saving said state information comprises saving a plurality of data addresses specified by said plurality of instructions.

34. The method of claim 33, further comprising:

determining whether one or more of said plurality of instructions specifies data in the data cache after termination of said stall condition.

35. The method of claim 34, wherein said determining whether one or more of said plurality of instructions specifies data in the data cache after termination of said stall condition comprises providing said plurality of data addresses to a cache memory in the data cache.

28. A method for resolving misses of a data cache in a single-issue in-order pipelined microprocessor during stalls of the microprocessor pipeline, the method comprising:

detecting a stall condition in said pipeline generated by an instruction issued by the single-issue microprocessor;

saving state information associated with a plurality of instructions issued subsequent to said instruction in response to said detecting said stall condition; and

determining whether one or more of said plurality of instructions specifies data missing in the data cache during said stall condition.