Test bus architecture for embedded RAM and method of operating same
First Claim
1. An integrated circuit chip comprising:
- a plurality of random access memory (RAM) blocks, wherein each of the RAM blocks is accessible by system circuitry located on the chip during normal operation of the chip;
a plurality of test modules, each being coupled to a corresponding one of the RAM blocks, wherein each of the test modules enables access to a corresponding one of the RAM blocks, independent of the system circuitry; and
a dedicated test bus coupled to each of the test modules.
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Abstract
An integrated circuit chip is provided having a plurality of embedded RAM/register blocks, a corresponding plurality of test modules, and a dedicated test bus. Each RAM/register block is coupled to a corresponding test module, as well as to system circuitry. Each test module is coupled to the test bus. The embedded RAM/register blocks are accessible through the system circuitry during normal operation. During a test mode the embedded RAM/register blocks are accessible through the test modules and test bus. During the test mode, test data values are written to the RAM/register blocks by broadcasting test data values to all of the RAM/register blocks on the test bus. Subsequently, the test data values are read from the RAM/register blocks by individually accessing the RAM/register blocks on the test bus. The test modules are assigned unique addresses, thereby enabling the RAM/register blocks to be addressed during the read operations.
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Citations
18 Claims
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1. An integrated circuit chip comprising:
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a plurality of random access memory (RAM) blocks, wherein each of the RAM blocks is accessible by system circuitry located on the chip during normal operation of the chip;
a plurality of test modules, each being coupled to a corresponding one of the RAM blocks, wherein each of the test modules enables access to a corresponding one of the RAM blocks, independent of the system circuitry; and
a dedicated test bus coupled to each of the test modules. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating RAM blocks having a capacity less of 32 Kb or less embedded in system circuitry on an integrated circuit chip, the method comprising the steps of:
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accessing the RAM blocks through the system circuitry during normal operation of the chip; and
accessing the RAM blocks through a dedicated test bus during a test mode to test the functionality of the RAM blocks prior to normal operation of the chip. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification