Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates and devices formed thereby

• US 20030010971A1
• Filed: 06/24/2002
• Published: 01/16/2003
• Est. Priority Date: 06/25/2001
• Status: Active Grant

• Current Assignee: North Carolina State University (University of North Carolina System)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Misra, Veena, Zhang, Zhibo, Ozturk, Mehmet, Bedair, Salah M. A.
• Granted Patent: US 6,709,929 B2
• Time in Patent Office: Days
• US Class Current: 257/15
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/125 Quantum wire structures
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Abstract

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

Claims

1. A method of forming a vertical nano-scale electronic device, comprising the steps of:

forming a substrate comprising a semiconductor layer and a substrate insulating layer on the semiconductor layer;

forming an etching template having a first array of non-photolithographically defined nano-channels extending therethrough, on the substrate insulating layer;

selectively etching the substrate insulating layer to define a second array of nano-channels therein, using the etching template as an etching mask; and

forming an array of semiconductor nano-pillars that extend in the second array of nano-channels and have an average diameter in a range between about 8 nm and about 50 nm.

2. The method of claim 1, wherein said step of forming an etching template comprises forming a nanoporous anodic aluminum oxide thin film on the substrate insulating layer.

3. The method of claim 1, wherein said step of forming an etching template comprises:

forming a metal film on the substrate insulating layer; and

anodizing the metal film into an anodic metal oxide layer.

4. The method of claim 1, wherein said selectively etching step comprises ion etching or reactive ion etching the substrate insulating layer for a sufficient duration to penetrate the substrate insulating layer.

5. The method of claim 1, wherein said selectively etching step comprises ion etching or reactive ion etching the substrate insulating layer for a sufficient duration to penetrate the substrate insulating layer and expose the semiconductor layer.

6. The method of claim 5, wherein the semiconductor layer is a monocrystalline semiconductor layer;

and wherein said step of forming an array of semiconductor nano-pillars comprises epitaxially growing monocrystalline semiconductor nano-pillars in the second array of nano-channels.

7. A method of claim 6, further comprising the steps of:

removing the substrate insulating layer to expose sidewalls of the semiconductor nano-pillars;

implanting dopants of first conductivity type into upper surfaces of the semiconductor nano-pillars to define respective drain regions therein;

forming gate insulating layers on the sidewalls of the semiconductor nano-pillars;

forming a gate electrode that extends on the gate insulating layers and in recesses between the semiconductor nano-pillars; and

forming a drain electrode that electrically contacts the drain regions in the semiconducting nano-pillars.

8. The method of claim 7, wherein said step of forming a drain electrode is preceded by the steps of:

depositing an electrically insulating passivation layer on the gate electrode; and

etching-back the passivation layer to expose the upper surfaces of the semiconducting nano-pillars.

9. The method of claim 7, wherein said implanting step is preceded by the steps of:

forming a sacrificial protective layer on upper surfaces and sidewalls of the semiconductor nano-pillars; and

etching-back the sacrificial protective layer to expose the upper surfaces of the semiconducting nano-pillars.

10. The method of claim 9, wherein said step of forming gate insulating layers is preceded by the step of removing the sacrificial protective layer.

11. The method of claim 7, wherein said implanting step is preceded by the steps of:

forming a sacrificial protective layer on upper surfaces and sidewalls of the semiconductor nano-pillars; and

etching-back the sacrificial protective layer to expose the upper surfaces of the semiconductor nano-pillars and expose portions of the underlying substrate.

12. The method of claim 11, wherein said step of forming gate insulating layers is preceded by the step of removing the sacrificial protective layer.

13. The method of claim 12, wherein said implanting step comprises implanting dopants of first conductivity type into the upper surfaces of the semiconductor nano-pillars and the exposed portions of the substrate to define drain and source regions therein.

14. A method of claim 1, further comprising the steps of:

removing the substrate insulating layer to expose sidewalls of the semiconductor nano-pillars;

implanting dopants of first conductivity type into upper surfaces of the semiconductor nano-pillars to define respective drain regions therein;

forming gate insulating layers on the sidewalls of the semiconductor nano-pillars;

forming a gate electrode that extends on the gate insulating layers and in recesses between the semiconductor nano-pillars; and

forming a drain electrode that electrically contacts the drain regions in the semiconducting nano-pillars.

16. The method of claim 15, wherein said step of forming an etching template comprises:

forming a metal film on the barrier metal layer;

anodizing the metal film into an anodic metal oxide layer; and

etching the barrier metal layer using the anodic metal oxide layer as an etching mask.

15. A method of forming a vertical nano-scale electronic device, comprising the steps of:

forming a substrate comprising a semiconductor layer, a substrate insulating layer on the semiconductor layer and a barrier metal layer on the substrate insulating layer;

forming an etching template having a first array of non-photolithographically defined nano-channels extending therethrough, on the substrate insulating layer;

selectively etching the substrate insulating layer for a sufficient duration to define a second array of nano-channels therein, using the etching template as an etching mask; and

forming an array of semiconductor nano-pillars that extend in the second array of nano-channels.

17. A method of forming a vertical nano-scale electronic device, comprising the steps of:

forming a substrate comprising a semiconductor layer and a non-aluminum barrier metal layer on the semiconductor layer;

forming an anodic aluminum oxide layer having an array of nano-sized pores therein, on the barrier metal layer;

selectively etching portions of the barrier metal layer extending adjacent bottoms of the nano-sized pores, using the anodic aluminum oxide layer as an etching mask; and

forming an array of semiconductor nano-pillars that extend in the nano-sized pores.

18. A method of forming a vertical nano-scale opto-electronic device, comprising the steps of:

forming a substrate comprising a first compound semiconductor layer of first conductivity type that is a composite of first and second III-V semiconductor materials;

forming an electrically insulating layer on the first compound semiconductor layer;

forming a metal thin film on the electrically insulating layer;

converting the metal thin film to an anodized metal oxide layer having an array of nanopores therein;

transferring the array of nanopores in the anodized metal oxide layer into the electrically insulating layer;

epitaxially growing an array of vertical quantum-dot superlattices in the array of nanopores in the electrically insulating layer; and

forming a second compound semiconductor layer of second conductivity type that is a composite of the first and second III-V semiconductor materials, on the array of vertical quantum-dot superlattices.

19. An opto-electronic device, comprising:

a substrate comprising a first III-V semiconductor layer;

an electrically insulating layer that extends on the first III-V semiconductor layer and comprises an array of non-photolithographically defined nanopores therein;

an array of vertical quantum-dot superlattices in the array of nanopores; and

a second III-V semiconductor layer on said array of vertical quantum-dot superlattices.

20. A method of forming a vertical nano-scale field effect transistor, comprising the steps of:

forming an electrically insulating layer having an array of nanopores therein;

forming an array of monocrystalline semiconductor nano-pillars in the array of nanopores;

forming a plurality of drain regions in the semiconductor nano-pillars; and

forming a gate electrode that at least partially surrounds the semiconductor nano-pillars.

21. A method of forming a vertical nano-scale field effect transistor array, comprising the steps of:

forming an array of semiconductor pillars that extend upward from an underlying substrate;

implanting source/drain region dopants into the array of semiconductor pillars and into the substrate to define a respective first source/drain region in each of a plurality of semiconductor pillars in the array and a second source/drain region that extends as a contiguous mesh in the substrate; and

forming a gate electrode that surrounds at least a plurality of the semiconductor pillars in the array.

22. A method of forming a vertical nano-scale opto-electronic device, comprising the steps of:

forming a substrate comprising a first compound semiconductor layer of first conductivity type that is a composite of first and second III-V semiconductor materials;

forming an anodized metal oxide layer having an array of nanopores therein, on the first compound semiconductor layer;

epitaxially growing an array of vertical quantum-dot superlattices in the array of nanopores, using the first compound semiconductor layer as a seed layer; and

forming a second compound semiconductor layer of second conductivity type that is a composite of the first and second III-V semiconductor materials, on the array of vertical quantum-dot superlattices.

23. The method of claim 22, wherein said step of forming an anodized metal oxide layer comprises epitaxially growing an aluminum metal layer on the first compound semiconductor layer.

24. The method of claim 23, wherein the first compound semiconductor layer comprises Al_xGa₁₋

xAs.

25. An opto-electronic device, comprising:

an electrically insulating layer having an array of non-photolithographically defined nanopores therein; and

an array of vertical quantum-dot compound semiconductor superlattices in the array of nanopores.