Equipment for and method of detecting faults in semiconductor integrated circuits

• US 20030011376A1
• Filed: 03/28/2002
• Published: 01/16/2003
• Est. Priority Date: 03/29/2001
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsushita, Hiroshi, Ushiku, Yukihiro, Mitsutake, Kunihiro
• Granted Patent: US 7,222,026 B2
• Time in Patent Office: Days
• US Class Current: 324/500
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An equipment for detecting faults in semiconductor integrated circuits includes a fault input unit to input fault information for the integrated circuits formed on a semiconductor wafer, a superimposing unit to superimpose the fault information with repeating units within the surface of the semiconductor wafer, and a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which faults are repeated every repeating unit.

Claims

1. An equipment for detecting faults in semiconductor integrated circuits comprising:

a fault input unit to input fault information for said semiconductor integrated circuits formed on a semiconductor wafer;

a superimposing unit to superimpose said fault information with repeating units within the surface of said semiconductor wafer; and

a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which faults are repeated every said repeating unit.

2. The equipment of claim 1, comprising an abnormal region removal unit to delete abnormal fault information from said fault information before superimposing said fault information with said repeating units.

3. The equipment of claim 1, comprising an abnormal region removal unit to determine a abnormal fault information, when total of said fault information input is greater than surrounding fault information.

4. The equipment of claim 2, wherein said abnormal region removal unit determines said abnormal fault information, when total of said fault information input is greater than surrounding fault information.

5. The equipment of claim 1, wherein said first characteristic factor calculation unit determines whether said faults are repeated every said repeating unit by comparing said first characteristic factor with a predetermined threshold value.

6. The equipment of claim 1, comprising:

a first data storage unit to register said faults that repeat every said repeating unit; and

a clustering factor calculation unit to calculate a second characteristic factor representing a degree of polarization in fault distribution within said semiconductor surface;

wherein

said first characteristic factor calculation unit determines whether said faults detected with said second characteristic factor but not detected with said first characteristic factor.

7. A method of detecting faults in semiconductor integrated circuits, comprising:

inputting fault information for said semiconductor integrated circuits formed on a semiconductor wafer;

superimposing said fault information with repeating units within the surface of said semiconductor wafer; and

calculating a first characteristic factor showing a degree to which faults are repeated every said repeating unit.

8. The method of claim 7, comprising deleting abnormal fault information from said fault information before superimposing said fault information with said repeating units.

9. The method of claim 8, comprising determining said abnormal fault information, when total of said fault information input is greater than surrounding fault information.

10. The method of claim 7, comprising determining whether said faults are repeated every said repeating unit by comparing said first characteristic factor with a predetermined threshold value.

11. The method of claim 8, comprising determining whether said faults are repeated every said repeating unit by comparing said first characteristic factor with a predetermined threshold value.

12. The method of claim 9, comprising determining whether said faults are repeated every said repeating unit by comparing said first characteristic factor with a predetermined threshold value.

13. The method of claim 7, comprising:

registering said faults that repeat every said repeating unit;

calculating a second characteristic factor representing a degree of polarization in fault distribution within said semiconductor surface; and

determining whether said faults detected with said second characteristic factor but not detected with said first characteristic factor.

14. The method of claim 7, comprising:

setting a fault region corresponding to one of fault modes within a vector space configured by vector comprising a plurality of said first characteristic factors; and

determining said fault mode in conformity with verification of said fault region and said vector.

15. The method of claim 14, comprising calculating third characteristic factors comprising a scalar amount showing a degree of said fault mode.

16. The method of claim 15, wherein said calculating third characteristic factors comprises:

setting an upper limit region, lower limit region, and threshold value region for the degree of said fault mode;

assigning said third characteristic factors to said upper limit region, said lower limit region, and said threshold value region; and

interpolating among said upper limit region, said lower limit region, and said threshold value region.

17. The method of claim 16, wherein said interpolating comprises linearly interpolating in terms of distance within said vector space.

18. The method of claim 14, wherein said plurality of the first characteristic factors comprises:

first characteristic factors to show a topology of said fault mode; and

first characteristic factors to show a position of said fault within said wafer surface.