Planar inductors and method of manufacturing thereof

• US 20030011458A1
• Filed: 07/12/2001
• Published: 01/16/2003
• Est. Priority Date: 07/12/2001
• Status: Active Grant

• Current Assignee: Custom One Design, Inc.
• Original Assignee: Custom One Design, Inc.
• Inventors: Nuytkens, Peter R., Kulinets, Joseph M., Popeko, Ilya E.
• Granted Patent: US 6,696,910 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 27/24 Magnetic cores
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/36 Electric or magnetic shields or screens movable for varying inductance H01F21/10
• CPC Class Codes: H01F 27/363 made of electrically conductive material
• CPC Class Codes: H01F 41/02 for manufacturing cores, coils, or magnets H01F41/14 takes precedence; for dynamo-electric machines H02K15/00
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/086 for inductive purposes, e.g. printed inductor with ferrite core
• CPC Class Codes: H05K 2201/097 Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components
• CPC Class Codes: H05K 2203/072 Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 3/184 using masks
• CPC Class Codes: H05K 3/381 by special treatment of the substrate
• CPC Class Codes: H05K 3/4614 : the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49073 : by assembling coil and core
• CPC Class Codes: Y10T 29/49075 : including permanent magnet or core
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A printed circuit board has two layers of printed circuit board dielectric material; a core made of ferromagnetic material between the two layers; and conductive leads on the opposite side of each dielectric layer from the core connected by via holes through both dielectric layers to form a conducting coil around the core. The conductive leads can form two separate coils around the core to form a transformer. A planar conducing sheet can be placed on or between one or more of the printed circuit board'"'"'s dielectric layers to shield other circuitry on the printed circuit board from magnetic fields generated around the core. The core can be formed at least in part by electroless plating. Electroplating can be used to add a thicker layer of less conductive ferromagnetic material. Ferromagnetic inductive cores can be formed on the surface of a dielectric material by: dipping the surface of the dielectric in a solution containing catalytic metal particles having a slight dipole; and placing the dielectric in a metal salt to cause a layer containing metal to be electrolessly plated upon the dielectric. Plasma etching or other technique can be used before the dipping process to roughen the dielectric'"'"'s surface to help attract the catalytic particles. This method can be used to form an inductor core on or between one or more dielectric layers of a printed circuit board, of a multichip module, of an integrated circuit, or of a micro-electromechanical device.

Claims

1. A printed circuit board comprising:

two layers of printed circuit board dielectric material;

a core made of ferromagnetic material between said two layers;

conductive leads on the opposite side of each dielectric layer from the core which are connected by via holes through both dielectric layers so as to form a conducting coil around the core.

2. A printed circuit board as in claim 1 wherein the conductive leads from two separate coils around the same core so that one such coil can act as a primary winding and the other can act as a secondary winding of a transformer.

3. A printed circuit board as in claim 1 wherein a planar conducing sheet is placed on or between one or more of the printed circuit board'"'"'s dielectric layers so as to shield other circuitry on the printed circuit board from magnetic fields generated around the core.

4. A printed circuit board as in claim 1 wherein the core is formed of two separate layer of ferromagnetic material, each formed at a corresponding locations on a facing side of one of said two dielectric layers.

5. A printed circuit board as in claim 1 wherein the core has been formed at least in part by electroless plating on one or both of said dielectric layers.

6. A printed circuit board as in claim 5 wherein said core has been deposited on one or more of said dielectric layers by a process comprising:

dipping the surface of the dielectric material in a solution containing catalytic metal particles which have a slight electrostatic dipole when in solution to help those particles attach to the dielectric material'"'"'s surface; and

placing the surface of the dielectric material in a first metal salt solution in metastable equilibrium with a reducing agent so as to cause a first layer containing metal to be plated upon the surface of the dielectric material containing the catalytic metal particles by a process of electroless plating.

7. A printed circuit board as in claim 5 further including, before dipping the dielectric material in the solution of catalytic metal particles, plasma etching the surface of the dielectric material to roughen its surface and to create peaks and valleys in the surface of that material which have van der Waal forces capable of attracting catalytic particles which have a slight electrostatic dipole.

8. A printed circuit board as in claim 7:

wherein said first layer is thin layer of relatively conductive metallic material used as a seed layer; and

the method further includes, after the formation of said seed layer, placing the surface of the dielectric material in a second metal salt solution in metastable equilibrium with a reducing agent which has a higher concentration of non-metal elements than said first solution so as to cause material to be plated upon the seed layer which is a ferromagnetic material having a lower conductivity than the material of said seed layer.

9. A method as in claim 7:

wherein said first layer is thin layer of relatively conductive metallic material used as a seed layer; and

the method further includes using electroplating to plate less conductive ferromagnetic material onto said seed layer.

10. A method of forming ferromagnetic inductive cores on the surface of a dielectric material comprising:

dipping the surface of the dielectric material in a solution containing catalytic metal particles which have a slight electrostatic dipole when in solution to help those particles attach to the dielectric material'"'"'s surface; and

placing the surface of the dielectric material in a first metal salt solution in metastable equilibrium with a reducing agent so as to cause a first layer containing metal to be plated upon the surface of the dielectric material containing the catalytic metal particles by a process of electroless plating.

11. A method as in claim 10 further including, before dipping the dielectric material in the solution of catalytic metal particles, plasma etching the surface of the dielectric material to roughen its surface and to create peaks and valleys in the surface of that material which have van der Waal forces capable of attracting catalytic particles which have a slight electrostatic dipole.

12. A method as in claim 11 wherein the plasma etching is non-reactive ion etching.

13. A method as in claim 10 wherein said ferromagnetic material is phosphorous doped nickel.

14. A method as in claim 10 wherein said ferromagnetic material is boron doped nickel.

15. A method as in claim 10 wherein the catalytic particles are particles selected from the group consisting of cobalt, palladium, ruthenium, rhodium, platinum, iridium, osmium, nickel, and iron.

17. A method as in claim 16 further including, before dipping the dielectric material in the solution of catalytic metal particles, plasma etching the surface of the dielectric material to roughen its surface and to create peaks and valleys in the surface of that material which have van der Waal forces capable of attracting catalytic particles which have a slight electrostatic dipole.

18. A method as in claim 17 wherein the plasma etching is non-reactive ion etching.

21. A method as in claim 16 wherein said method is used to form an inductor core on or between one or more dielectric layers of a printed circuit board.

22. A method as in claim 16 wherein said method is used to form an inductor core on or between one or more dielectric layers of a multichip module.

23. A method as in claim 16 wherein said method is used to form an inductor core on or between one or more dielectric layers of an integrated circuit.

24. A method as in claim 16 wherein said method is used to form an inductor core on or between one or more dielectric layers of a micro-electromechanical device, and said inductor is used to provide electromagnectically induced movement to a mechanical element of that device.

16. A method of forming ferromagnetic inductive cores on the surface of a dielectric material comprising:

dipping the surface of the dielectric material in a solution containing catalytic metal particles which have a slight electrostatic dipole when in solution to help those particles attach to the dielectric material'"'"'s surface; and

placing the surface of the dielectric material in a first metal salt solution in metastable equilibrium with a reducing agent so as to cause a first layer containing metal to be plated upon the surface of the dielectric material containing the catalytic metal particles by a process of electroless plating.

19. A method as in claim 16:

wherein said first layer is thin layer of relatively conductive metallic material used as a seed layer; and

the method further includes, after the formation of said seed layer, placing the surface of the dielectric material in a second metal salt solution in metastable equilibrium with a reducing agent which has a higher concentration of non-metal elements than said first solution so as to cause material to be plated upon the seed layer which is a ferromagnetic material having a lower conductivity than the material of said seed layer.

20. A method as in claim 16:

wherein said first layer is thin layer of relatively conductive metallic material used as a seed layer; and

the method further includes using electroplating to plate less conductive ferromagnetic material onto said seed layer.