Memory and method for replacing defective memory cells in the same

• US 20030012066A1
• Filed: 07/15/2002
• Published: 01/16/2003
• Est. Priority Date: 07/13/2001
• Status: Abandoned Application

• Current Assignee: Peter Poechmueller
• Original Assignee: Peter Poechmueller
• Inventors: Poechmueller, Peter
• Application Number:
  US10/195,753
• Publication Number:
  US 20030012066A1
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A memory wherein defective memory cells may be replaced includes a first memory region having at least one memory cell with an associated bit line, a second memory region having at least one memory cell with an associated bit line and a world line associated at least with the memory cell of the first memory region and the memory cell of the second memory region. Further, at least one redundant memory cell having an associated bit line and a means is provided to selectively couple the bit line of the redundant memory cell to the bit line of the memory cell of the first memory region or to the bit line of the memory cell of the second memory region in order to replace a defective memory cell in the first memory region or a defective memory cell in the second memory region.

Claims

1. A memory, comprising

a first memory region having at least one memory cell with an associated bit line;

a second memory region having at least one memory cell with an associated bit line;

a word line at least associated with the memory cell of the first memory region and with the memory cell of the second memory region;

at least one redundant memory cell having one associated bit line; and

a means in order to selectively couple the bit line of the redundant memory cell to the bit line of the memory cell of the first memory region or to the bit line of the memory cell of the second memory region in order to replace a defective memory cell in the first memory region or a defective memory cell in the second memory region.

2. The memory according to claim 1 having a control means operatively connected to the coupling means in order to output a control signal to the coupling means controlling the coupling of the bit line of the redundant memory cells to one of the bit lines of the memory cells of the memory regions.

3. The memory according to claim 1, comprising

a first data bus associated with the bit line of the memory cell of the first memory region;

a second data bus associated with the bit line of the memory cell of the second memory region;

a third data bus associated with the bit line of the redundant memory cell; and

a fourth data bus that outputs data from the memory;

wherein the coupling means selectively couples the first data bus or the third data bus to the fourth data bus or selectively couples the second data bus or the third data bus to the fourth data bus.

4. The memory according to claim 3, wherein the coupling means comprises a first change-over switch and a second change-over switch,

wherein the first change-over switch includes two inputs connected to the first data bus and to the third data bus and an output connected to the fourth data bus,

wherein the second change-over switch includes two inputs connected to the second data bus and to the third data bus and an output connected to the fourth data bus,

wherein the first and the second change-over switch receive the control signal and connect the first or third data bus and/or the second or the third data bus to the fourth data bus depending on the signal.

5. The memory according to claim 4, wherein the control means includes a first logic circuit and a second logic circuit,

wherein the first logic circuit is associated with the first change-over switch and outputs a first control signal to the same;

wherein the second logic circuit is associated with the second change-over switch and outputs a second control signal to the same.

6. The memory according to claim 1, having a plurality of redundant memory cells with associated bit lines, wherein the first and the second memory region respectively include a plurality of memory cells with associated bit lines.

7. The memory according to claim 6, having a plurality of word lines associated with memory cells of the first memory region and the memory cells of the second memory region.

8. The memory according to claim 1, wherein the memory cells in the first memory region and the memory cells in the second memory region may be read out simultaneously, wherein data from the first memory region and data from the second memory region are combined to a common data word for an output from the memory.

9. The memory according to claim 8, wherein the fourth data bus comprises a first portion connected to the coupling means in order to receive data from the first data bus or from the third data bus, and wherein the fourth data bus comprises a second portion connected to the coupling means in order to receive data from the second data bus or from the third data bus.

10. The memory according to claim 9, wherein the output of the first change-over switch is connected to the first portion of the fourth data bus and wherein the output of the second change-over switch is connected to the second portion of the fourth data bus.

11. The memory according to claim 6, wherein a predetermined number of the plurality of memory cells of the first memory region are combined, wherein a predetermined number of the plurality of memory cells of the second memory region are combined, and wherein a predetermined number of the plurality of redundant memory cells are combined, wherein the combined memory cells are simultaneously activable for reading out data, wherein the coupling means selectively couples the bit lines of the combined redundant memory cells to the bit lines of the combined memory cells of the first memory region or to the bit lines of the combined memory cells of the second memory region.

12. The memory according to claim 11, wherein one common activation line is each associated with the combined memory cells.

13. The memory according to claim 11, wherein the coupling means is operative to selectively couple individual bit lines of the combined redundant memory cells individual bit lines of the combined memory cells of the first memory region and the second memory region.

14. A method for replacing defective memory cells in a memory including a first memory region having a memory cell with an associated bit line, a second memory region having a memory cell with an associated bit line, a word line at least associated with the memory cell of the first memory region and the memory cell of the second memory region, and at least one redundant memory cell having an associated bit line, wherein the method includes the following step:

selectively coupling the bit line of the redundant memory cell to the bit line of the memory cell of the first memory region or to the bit line of the memory cell of the second memory region in order to replace a defective memory cell in the first memory region or a defective memory cell in the second memory region.