Method for synchronisation of two devices or apparatus connected to a telephone line

• US 20030012317A1
• Filed: 08/21/2002
• Published: 01/16/2003
• Est. Priority Date: 12/28/2000
• Status: Abandoned Application

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Delbecq, Dominique, Courtois, Fernand
• Application Number:
  US10/204,655
• Publication Number:
  US 20030012317A1
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04J 3/0614 the synchronising signal being characterised by the amplitude, duration or polarity
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Abstract

The present invention relates to a method for synchronisation of at least one first device or apparatus (6) with at least one second device or apparatus(7), comprising respectively a first (8) and a second (10) counter modulus n, and which are designed to exchange data by means of a galvanic connection.

The method according to the invention comprises the following steps:

generation by the second device or apparatus (7) of a clock signal, which acts as a counting basis for the second counter (10);

transmission of this clock signal to the first device or apparatus (8); and

transmission of the data of the second device or apparatus (7) to the first device or apparatus (6), at instants which are separated by at least two cycles of the clock signal, and, each time the second counter (10) is re-initialised, transmission to the first device or apparatus (6) of a synchronisation signal comprising two successive time slots of the clock signal.

Claims

1. A method for synchronisation of at least one first device or apparatus (6) with at least one second device or apparatus (7), comprising respectively a first (8) and a second (10) counter modulus n, and which are designed to exchange data via a galvanic connection, which method is characterized in that it comprises the following steps:

generation by the second device or apparatus (7) of a clock signal which acts as a counting basis for the second counter (10);

transmission of this clock signal to the first device or apparatus (6); and

transmission of the data from the second device or apparatus (7) to the first device or apparatus (6), at instants which are separated by at least two cycles of the clock signal, and, each time that the second counter (10) is re-initialised, transmission to the first device or apparatus of a synchronisation signal comprising two successive time slots of the clock signal.

2. A method as claimed in claim 1, characterised in that the galvanic connection is provided by means of three high-voltage capacitors C1, C2 and C3, the capacitors C1 and C2 being designed to transmit from the second device or apparatus (7) to the first device or apparatus (6), n−

2 successive cycles of the clock signal, the capacitor C3 being designed in particular to transmit the following successive two cycles n−

1 and n of the clock signal.

3. A method as claimed in claim 1, characterized in that the first device or apparatus (6) is an interface, which is designed to connect one or a plurality of devices or apparatus to a telephone line (4), the second device or apparatus (7) being a micro-controller.

4. A method as claimed in claim 3, characterized in that the micro-controller (7) transmits continually, and in a loop, to the line interface (6), for n−

2 cycles of the clock signal, a first data packet (TX), which is provided with a first address, and receives in return from the line interface (6) a second data packet (RX), which is provided with a second address, and detects a transmission fault on the line, if the first and the second addresses are different.

5. A method as claimed in claim 4, characterized in that the first and second ackets (TX) and (RX) comprise respectively the contents of a control register and a state register, as well as a memory address which is associated with each register, the first data packet additionally comprising a synchronisation key.

6. A method as claimed in claim 5, characterized in that the line interface (6) detects the synchronisation key, decodes the memory address of each register, and returns the content of the state register, which is provided with the same address, in the memory of the micro-controller (7).

7. A method as claimed in claim 6, characterized in that the contents of each control register and each state register of are validated by an error detector code.

8. A method as claimed in claim 7, characterized in that, before the connection is established between the line interface (6) and the micro-controller (7), the latter transmits to the line interface (6) a specific binary frame, which makes it possible to initialise the exchange of data, and in that, if there is a fault on the line, the line interface (6) returns to the micro-controller (7) state data comprising at least one error indication bit.