Method of fabricating a self-aligned non-volatile memory cell

• US 20030013255A1
• Filed: 09/06/2002
• Published: 01/16/2003
• Est. Priority Date: 11/30/2000
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil, Renninger, Alan L.
• Granted Patent: US 6,624,029 B2
• Time in Patent Office: Days
• US Class Current: 438/266
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Claims

1. A method of fabricating a self-aligned non-volatile memory cell on a semiconductor substrate, said method comprising the steps of:

forming a first insulating layer over said substrate;

forming a main floating gate region on said first insulating layer;

modifying a first portion of said first insulating layer next to a side of said main floating gate region to form a thin insulating region, said thin insulating region being thinner than a second portion of said first insulating layer under said main floating gate region;

forming a small sidewall spacer over said thin insulating region;

forming a second insulating layer over said first insulating layer and over said small sidewall spacer;

removing a portion of said second insulating layer and said thin insulating region over said main floating gate region to expose a surface on top of said main floating gate region;

forming a thin connecting layer over and in physical contact with both said small sidewall spacer and said main floating gate region, said thin connecting layer contacting said main floating gate region via said surface, whereby said small sidewall spacer is electrically connected to said main floating gate region, and whereby said main floating gate region, said small sidewall spacer and said thin connecting layer form a floating gate of said non-volatile memory cell;

forming a third insulating layer over at least said floating gate; and

forming a control gate over said second insulating layer and above at least said floating gate.

2. The method of claim 1 wherein modifying a first portion of said first insulating layer comprises the steps of:

removing said first portion of said first insulating layer; and

forming said thin insulating region where said first portion of said first insulating layer once was.

3. The method of claim 2 wherein forming a small sidewall spacer comprises the steps of:

forming a conducting layer over at least said thin insulating region; and

etching said conducting layer to form said small sidewall spacer.

4. The method of claim 3 wherein said etching conducting layer comprises anisotropically etching.

5. The method of claim 1 wherein forming said thin insulating region comprises the step of forming a thin insulating layer at least over the place where said first portion of said first insulating layer once was and over said main floating gate region.

6. The method of claim 5 wherein forming a small sidewall spacer comprises the steps of:

forming a conducting layer over at least said thin insulating region; and

etching said conducting layer to form said small sidewall spacer.

7. The method of claim 6 wherein etching said conducting layer comprises anisotropically etching.

8. The method of claim 7 wherein forming a second insulating layer comprises forming an Oxide/Nitride/Oxide (ONO) layer.

9. The method of claim 1 wherein forming a small sidewall spacer comprises the steps of:

forming a conducting layer over at least said thin insulating region; and

etching said conducting layer to form said small sidewall spacer.

10. The method of claim 9 wherein etching said conducting layer comprises anisotropically etching.

11. The method of claim 1 wherein removing a portion of said thin insulating layer over said main floating gate region comprises using photoresist masks and wet-etch to help remove said portion of said thin insulating layer.

12. The method of claim 1 wherein removing a portion of said thin insulating layer over said main floating gate region comprises using a chemical mechanical polishing process to remove said portion of said thin insulating layer.