Power dissipation reduction in medical devices using adiabatic logic

• US 20030014082A1
• Filed: 04/30/2002
• Published: 01/16/2003
• Est. Priority Date: 10/28/1998
• Status: Abandoned Application

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Schu, Carl A., Thompson, David L.
• Application Number:
  US10/136,776
• Publication Number:
  US 20030014082A1
• Time in Patent Office: Days
• US Class Current: 607/5
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 19/0019 by energy recovery or adiabatic operation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for minimizing power dissipation within an implantable medical device through use of adiabatic logic is disclosed. The system includes a first and a second sub-circuit of the implantable medical device. An electrical connection interconnects the first and the second sub-circuits, the electrical connection including a capacitive element. Circuitry, which charges the capacitive element of the electrical connection to generate a ramp logic signal, is connected to the capacitive element. The ramp logic signal includes a frequency of less than 500 kilohertz, thereby creating a low frequency, low power system which reduces energy dissipation to the surrounding environment.

Claims

1. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:

a capacitive element associated with a bus within the implantable medical device, wherein the capacitive element is operatively coupled to a first potential;

N voltage supplies;

N switches corresponding to the N voltage supplies, each switch being operatively coupled between a corresponding one of the N voltage supplies and the capacitive element;

a first switch operatively coupled in parallel with the capacitive element between the N switches and the first potential; and

a controller operatively coupled to the N switches and to the first switch to control the N switches and the first switch.

2. The system of claim 1, wherein the capacitive element includes an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.

3. The system of claim 2, wherein the logic signal generated across the capacitive element is provided to the first electrical component.

4. The system of claim 2, wherein the logic signal generated across the capacitive element is provided to the second electrical component.

5. The system of claim 1, wherein the logic signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.

6. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:

a first switch operatively coupled to a first voltage potential;

a capacitive element associated with a bus within the implantable medical device operatively coupled to a second voltage potential;

a second switch operatively coupled to the second voltage potential in parallel with the capacitive element;

N parallel capacitors operatively coupled to the first voltage potential;

N parallel switches corresponding to the N parallel capacitors, each switch being operatively coupled between a corresponding one of the N capacitors and the capacitive element; and

a controller operatively coupled to the first switch, the second switch, and the N parallel switches to control the first switch, the second switch, and the N switches.

7. The system of claim 6, wherein the capacitive element has an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.

8. The system of claim 7, wherein the logic signal generated across the capacitive element is provided to the first electrical component.

9. The system of claim 7, wherein the logic signal generated across the capacitive element is provided to the second electrical component.

10. The system of claim 6, wherein the logic signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.

11. A system for generating a voltage signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:

a first current source operatively coupled to a first voltage potential;

a second current source operatively coupled to a second voltage potential;

a capacitive element associated with a bus within the implantable medical device operatively coupled to the second voltage potential;

a switch operatively coupled between the capacitive element and the first and second current sources for operatively coupling one of the first and second current sources to the capacitive element; and

a controller operatively coupled to the switch to control the switch.

12. The system of claim 11, wherein the capacitive element has an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.

13. The system of claim 12, wherein the voltage signal generated across the capacitive element is provided to the first electrical component.

14. The system of claim 12, wherein the voltage signal generated across the capacitive element is provided to the second electrical component.

15. The system of claim 11, wherein the voltage signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.

17. The system of claim 16, wherein the logic signal generated at the output of the buffer operates at a frequency of less than 500 kilohertz.

20. The method of claim 19, wherein the step of charging a capacitive element further comprises the step of:

charging an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.

21. The method of claim 20, wherein the step of supplying the logic signal further comprises the step of:

supplying the logic signal to the first electrical component.

22. The method of claim 20, wherein the step of supplying the logic signal further comprises the step of:

supplying the logic signal to a second electrical component.

23. The method of claim 19, wherein the step of charging a capacitive element further comprises the step of:

charging a capacitive element associated with a bus to generate a logic signal which operates at a frequency of less than 500 kilohertz.

16. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:

a clock having an output clock signal;

an inverter having an input, an output, and a resistance, wherein the output clock signal of the clock is operatively coupled to the input of the inverter;

an inductive element operatively coupled to the output of the inverter;

a buffer having an input, an internal input capacitance, and an output, wherein the input is operatively coupled to the inductive element; and

wherein the logic signal is generated at the output of the buffer and is provided to a portion of the implantable medical device.

18. An implantable medical device having an adiabatic scheme which is provided to a portion of an implantable medical device and which minimizes power dissipation from a sub-component of the implantable medical device, the implantable medical device comprising:

a first sub-circuit;

a second sub-circuit;

an electrical connection between the first and second sub-circuits, the. electrical connection including a capacitive element;

means for generating a logic signal having a frequency of less than 500 kilohertz, the logic signal including a plurality of repeating cycles, each cycle further comprising;

a first cycle portion where the ramped logic signal is at a first voltage;

a second cycle portion where the ramped logic signal is ramped from the first voltage to a second voltage;

a third cycle portion where the logic signal is at the second voltage;

a fourth cycle portion where the logic signal is ramped from the second voltage to the first voltage; and

means for supplying the logic signal to one of the first and second sub-circuits.

19. A method of generating a logic signal for a portion of an implantable medical device which minimizes power dissipation within the implantable medical device, the method comprising:

charging a capacitive element associated with a bus to generate a logic signal including a plurality of repeating cycles, each cycle comprising;

a first cycle portion where the logic signal is at a first voltage;

a second cycle portion where the ramped logic signal is ramped from the first voltage to a second voltage;

a third cycle portion where the logic signal is at the second voltage;

a fourth cycle portion where the logic signal is ramped from the second voltage to the first voltage; and

supplying the logic signal to the portion of the implantable medical device.