Alerting system, architecture and circuitry

• US 20030014517A1
• Filed: 04/24/2002
• Published: 01/16/2003
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Naylor, Andrew M., Lindsay, Steven B.
• Granted Patent: US 8,127,015 B2
• Time in Patent Office: Days
• US Class Current: 709/224
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 41/08 Configuration management of networks or network elements address allocation H04L61/50
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/082 the condition being updates or upgrades of network functionality
• CPC Class Codes: H04L 41/0856 by backing up or archiving configuration information
• CPC Class Codes: H04L 41/0869 Validating the configuration within one network element
• CPC Class Codes: H04L 41/147 for predicting network behaviour
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method for supporting ASF in an ASD using one or more embedded processors. In one aspect of the invention the method comprises accepting ASF related packets, examining the ASF related packets using a firmware routine running on the one or more embedded processors, and generating a response. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A method for supporting ASF in an ASD using one or more embedded processors, the method comprising:

providing a packet stream having both ASF and non ASF packets;

filtering and separating the ASF packets from the non-ASF packets;

accepting the ASF related packets to be processed;

examining the ASF related packets using a firmware routines running on the one or more embedded processors; and

generating an appropriate response.

2. A method as in claim 1 wherein the filtering of ASF packets comprises comparing packets in the packet stream in a programmable pattern detector.

3. The method of claim 1 wherein the one or more embedded processors comprise two embedded processors operating in parallel.

4. The method of claim 1 wherein the one or more embedded processors are running different aspects of the ASF protocol.

5. The method of claim 4 wherein examining the ASF related packets comprises interpreting a RMCP (Remote Management Control Protocol) packet.

6. The method of claim 5 wherein examining the ASF related packets comprises interpreting a SMBus message.

7. The method of claim 1 wherein examining the ASF related packets comprises interpreting a ASF packet.

8. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a PET (Platform Event Trap) packet.

9. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a RMCP response packet.

10. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a SMbus response.

11. A method for processing communications packets in an ASD, the method comprising:

accepting a sequence of packets, the sequence of packets including a plurality of types of packets;

detecting ARP (Address Resolution Protocol) packets;

removing the ARP packets from the sequence of a plurality of types of packets, without affecting or slowing down the non ASF packets; and

notifying at least one processor to process the ARP packets.

12. The method of claim 11 wherein detecting ARP packets comprises:

accepting the packets in a rules checker; and

comparing the packets to the rules, defining ARP packets, in the rules checker.

13. The method of claim 11 wherein removing the ARP packets from the sequence of a plurality of types of packets comprises inserting the ARP packets into a queue for processing by an internal processor.

14. The method of claim 11 wherein processing a response to the ARP packets comprises:

generating an ARP response transmit packet; and

transmitting the ARP response transmit packet.

16. The method of claim 15 wherein detecting RMCP packets comprises:

accepting the packets in a rules checker; and

comparing the packets to the rules, defining RMCP packets, in the rules checker.

17. The method of claim 15 wherein removing the RMCP packets from the sequence of a plurality of types of packets comprises inserting the RMCP packets into a queue for processing by an internal processor.

18. The method of claim 15 wherein processing a response to the RMCP packets comprises:

generating an RMCP response transmit packet; and

transmitting the RMCP response transmit packet.

20. The method of claim 19 wherein examining the indication of timer expiration of at least one of the timers comprises examining the indication during an idle loop of an embedded processor.

21. The method of claim 20 wherein examining the indication of timer expiration comprises examining the indication of status bits in an internal register.

22. The method of claim 19 wherein providing a plurality of hardware timers further comprises providing at least one time selected from the group of ASF timers consisting of a watchdog timer, a heartbeat timer, an ASF Sensor Poll Interval timer, a legacy sensor poll timer, a PET Re-transmission timer and a timestamp timer.

23. The method as in claim 19 wherein the indication of timer expiration is examined by at least one embedded processor.

24. The method of claim 19 wherein the timers are timed from a fixed clock source, which is not slowed when chip timing is slowed.

25. The method of claim 19 wherein the timers are timed from a fixed clock source, which does not vary dependant on link speed of the chip, or presence of PCI power.

26. The method of claim 19 wherein the timers are timed from a fixed clock source, which does not vary with PCI power presence.

15. A method for processing communications packets in an ASD, the method comprising:

accepting a sequence of packets, the sequence of packets including a plurality of types of packets;

detecting RMCP (Remote Management and Control Protocol) packets;

removing the Remote Management and Control Protocol (RMCP) packets from the sequence of a plurality of types of packets, without affecting or slowing down the non RMCP packets; and

notifying at least one processor to process the RMCP packets.

19. A method of providing ASF timers the method comprising:

providing a plurality of hardware timers;

loading the timers with a count;

starting the timers counting;

creating an indication of timer expiration on expiration of the count for each timer; and

examining the indication of timer expiration of at least one of the timers.

27. A method for supporting ASF in an ASD using one or more embedded processors, the method comprising:

providing a packet stream having both ASF and non ASF packets;

filtering and separating the ASF packets from the non-ASF packets;

accepting the ASF related packets to be processed;

examining the ASF related packets using a firmware routines running on the one or more embedded processors; and

generating an appropriate response.

28. An apparatus for processing communications packets in an ASD, the apparatus comprising:

an input for accepting a sequence of packets, the sequence of packets including a plurality of types of packets;

a pattern matching circuit for detecting ARP (Address Resolution Protocol) packets;

a queue for placing the detected ARP packets in; and

at least one processor to remove the ARP packets from the queue and process the ARP packets.

29. An apparatus for processing communications packets in an ASD, the apparatus comprising:

an input for accepting a sequence of packets, the sequence of packets including a plurality of types of packets;

a pattern matching circuit for detecting RMCP packets;

a queue for placing the detected RMCP packets in; and

at least one processor to remove the RMCP packets from the queue and process the RMCP packets.

30. An apparatus for providing ASF timers the apparatus comprising:

a plurality of hardware timers;

at least one embedded processor, which loads the timers with a count;

at least one embedded processor, which and starts the timers counting;

a register for receiving an indication of timer expiration on expiration of the count for each timer; and

at least one embedded processor, which examines the indication of timer expiration of at least one of the timers.