MECHANISM FOR PROGRAMMABLE MODIFICATION OF MEMORY MAPPING GRANULARITY

• US 20030014609A1
• Filed: 07/13/2001
• Published: 01/16/2003
• Est. Priority Date: 07/13/2001
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Granted Patent: US 6,523,104 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page table entries (PTEs) and a pagegrain register for prescribing a minimum page size. Each of the PTEs in the MMU specifies a page granularity for a corresponding physical memory page, where the page granularity is bounded by the minimum page size. The MMU has and page granularity logic. The page granularity logic determines a page size for the corresponding physical memory page. The page size is determined based on the minimum page size and the page granularity. The pagegrain register prescribes the minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol.

Claims

1. An apparatus for providing programmable minimum memory page sizes, the apparatus comprising:

a pagegrain register, configured to prescribe a minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol; and

a memory management unit (MMU), coupled to said pagegrain register, configured to store a plurality of page table entries (PTEs), each of said plurality of PTEs specifying a page granularity for a corresponding physical memory page, wherein said page granularity is bounded by said minimum page size, said MMU comprising;

page granularity logic, configured to determine a page size for said corresponding physical memory page, wherein said page size is determined based on said minimum page size and said page granularity.

2. The apparatus as recited in claim 1, wherein said minimum page size according to said legacy memory management protocol is 4 KB.

3. The apparatus as recited in claim 2, wherein the programmable minimum memory page sizes according to said extended memory management protocol comprise a 1 KB minimum page size, a 2 KB minimum page size, and a 4 KB minimum page size.

4. The apparatus as recited in claim 1, wherein said pagegrain register is programmed to prescribe said one of the programmable minimum memory page sizes by execution of an instruction in accordance with said extended memory management protocol.

5. The apparatus as recited in claim 4, wherein said each of said plurality of PTEs comprises a physical frame number (PFN) field, and wherein bits of said PFN field are employed to construct an upper part of a physical address associated with said corresponding physical memory page.

6. The apparatus as recited in claim 5, wherein said MMU further comprises:

physical address construction logic, coupled to said page granularity logic, configured to construct said upper part, and a lower part of said physical address using lower bits of a virtual address, wherein said page size determines how many of said lower bits are used to construct said lower part, and the positions within said upper part that are occupied by bits taken from said physical frame number field.

7. The apparatus as recited in claim 6, wherein said MMU further comprises:

a translation lookaside buffer (TLB), coupled to said physical address construction logic, configured to store frequently used ones of said plurality of PTEs, and configured to provide said PFN field for construction of said upper part of said physical address.

8. The apparatus as recited in claim 7, wherein said TLB comprises a software-based TLB.

9. The apparatus as recited in claim 7, wherein said TLB comprises a hardware-based TLB.

10. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium, having computer readable program code embodied in said medium, for causing a CPU to be described, said CPU being capable of sizing memory pages according to a legacy memory management technique or an extended memory management technique, said computer readable program code comprising;

first program code, for describing a memory management unit (MMU), said MMU configured to store page table entries (PTEs), each of said PTEs prescribing a page granularity for a corresponding physical memory page, wherein said page granularity is bounded by a minimum page size;

second program code, for describing page granularity logic within said MMU, and being configured to establish a page size for said corresponding physical memory page, wherein said page size is established as a function of a minimum page size and said page granularity; and

third program code, for describing a pagegrain register, said pagegrain register being coupled to said MMU, said pagegrain register configured to specify said minimum page size, in default, according to said legacy memory management technique, and in alternative, according to said extended memory management technique.

11. The computer program product as recited in claim 10, wherein said minimum page size according to said legacy memory management technique is 4 KB.

12. The computer program product as recited in claim 10, wherein said minimum page size according to said extended memory management technique can be programmed to either 1 KB, 2 KB, or 4 KB.

13. The computer program product as recited in claim 12, wherein said pagegrain register is programmed to prescribe said minimum page size via execution of an instruction according to said extended memory management technique.

14. The computer program product as recited in claim 13, wherein said each of said PTEs comprises a physical frame number (PFN) field, and wherein bits of said PFN field are employed to construct an upper part of a physical address associated with said corresponding physical memory page.

15. The computer program product as recited in claim 14, further comprising:

fourth program code, for describing physical address construction logic within said MMU, said physical address construction logic being coupled to said page granularity logic, and being configured to construct said upper part, and a lower part of said physical address using lower bits of a virtual address, wherein said page size determines how many of said lower bits are used to construct said lower part, and the positions within said upper part that are occupied by bits taken from said physical frame number field.

16. The computer program product as recited in claim 15, further comprising:

fifth program code, for describing a translation lookaside buffer (TLB) within said MMU, coupled to said physical address construction logic, configured to store frequently used ones of said PTEs, and configured to provide said PFN field for construction of said upper part of said physical address.

17. The computer program product as recited in claim 16, wherein said TLB comprises a software-based TLB.

18. The computer program product as recited in claim 16, wherein said TLB comprises a hardware-based TLB.

20. The computer data signal as recited in claim 19, wherein said minimum page size according to said legacy memory management protocol is 4 KB.

21. The computer data signal as recited in claim 19, wherein said minimum page size according to said extended memory management protocol can be programmed to either 1 KB, 2 KB, or 4 KB.

22. The computer data signal as recited in claim 21, wherein said pagegrain register is programmed to prescribe said minimum page size via execution of an instruction according to said extended memory management protocol.

23. The computer data signal as recited in claim 22, wherein said each of said PTEs comprises a physical frame number (PFN) field, and wherein bits of said PFN field are employed to construct an upper part of a physical address associated with said corresponding physical memory page.

24. The computer data signal as recited in claim 23, further comprising:

fourth computer-readable program code, for describing physical address construction logic within said MMU, said physical address construction logic being coupled to said page granularity logic, and being configured to construct said upper part, and a lower part of said physical address using lower bits of a virtual address, wherein said page size determines how many of said lower bits are used to construct said lower part, and the positions within said upper part that are occupied by bits taken from said physical frame number field.

25. The computer data signal as recited in claim 24, further comprising:

fifth computer-readable program code, for describing a translation lookaside buffer (TLB) within said MMU, coupled to said physical address construction logic, configured to store frequently used ones of said PTEs, and configured to provide said PFN field for construction of said upper part of said physical address.

26. The computer data signal as recited in claim 25, wherein said TLB comprises a software-based TLB.

27. The computer data signal as recited in claim 25, wherein said TLB comprises a hardware-based TLB.

29. The method as recited in claim 28, wherein said initiating sets the minimum page size to 4 KB.

30. The method as recited in claim 28, wherein said programming sets the minimum page size to either 1 KB, 2 KB, or 4 KB.

31. The method as recited in claim 28, wherein said programming comprises:

executing an instruction in accordance with said extended memory management protocol.

32. The method as recited in claim 28, wherein said storing comprises:

within the each of the PTEs, employing a physical frame number (PFN) field, wherein bits of the PFN field are used to generate an upper part of a physical address associated with the corresponding physical memory page.

33. The method as recited in claim 32, further comprising:

first constructing the upper part, wherein the page size determines positions within the upper part that are occupied by bits taken from the physical frame number field; and

second constructing a lower part of the physical address using lower bits of a virtual address, wherein the page size determines how many of the lower bits are used to construct the lower part.

34. The method as recited in claim 28, wherein said storing comprises:

employing a translation lookaside buffer (TLB) that is configured to store frequently used PTEs; and

from the TLB, providing said PFN field for construction of said upper part of said physical address.

35. The method as recited in claim 34, wherein said TLB is a software-based TLB.

36. The method as recited in claim 34, wherein said TLB is a hardware-based TLB.

19. A computer data signal embodied in a transmission medium, comprising:

first computer-readable program code, for describing a memory management unit (MMU), said MMU configured to store page table entries (PTEs), each of said PTEs specifying a page granularity for a corresponding physical memory page, wherein said page granularity is bounded by a minimum page size;

second computer-readable program code, for describing page granularity logic within said MMU, said page granularity logic configured to determine a page size for said corresponding physical memory page, wherein said page size is determined based on said minimum page size and said page granularity; and

third computer-readable program code, for describing a pagegrain register coupled to said MMU, said pagegrain register configured to prescribe said minimum page size, in default, according to a legacy memory management protocol, and in alternative, according to an extended memory management protocol.

28. A method for providing programmable minimum memory page sizes, the method comprising:

within a memory management unit (MMU), storing page table entries (PTEs), wherein each of the PTEs prescribes a page granularity for a corresponding physical memory page, and wherein the page granularity is bounded by a minimum page size;

initiating contents of a pagegrain register to designate the minimum page size such that address translation comports with a legacy memory management protocol;

programming the contents of the pagegrain register to designate the minimum page size such that address translation comports with an extended memory management protocol; and

determining a page size for the corresponding physical memory page based on the page granularity and said programming.

37. A virtual memory system, for providing programmable minimum memory page sizes, the virtual memory system comprising:

a central processing unit (CPU), for accessing instructions/data within a physical memory, wherein access of said instructions/data is controlled according to a legacy virtual memory management protocol or an extended virtual memory management protocol, said CPU comprising;

a pagegrain register, configured to prescribe a minimum page size, in default, according to said legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to said extended memory management protocol; and

a memory management unit (MMU), coupled to said pagegrain register, configured to store a plurality of page table entries (PTEs), each of said plurality of PTEs specifying a page granularity for a corresponding physical memory page, wherein said page granularity is bounded by said minimum page size, said MMU comprising;

page granularity logic, configured to determine a page size for said corresponding physical memory page, wherein said page size is determined based on said minimum page size and said page granularity.