POWER SYSTEM TIME SYNCHRONIZATION DEVICE AND METHOD FOR SEQUENCE OF EVENT RECORDING

• US 20030014678A1
• Filed: 08/09/1999
• Published: 01/16/2003
• Est. Priority Date: 08/09/1999
• Status: Active Grant

• Current Assignee: Power Measurement Ltd. (Schneider Electric SE)
• Original Assignee: Power Measurement Ltd. (Schneider Electric SE)
• Inventors: LIGHTBODY, SIMON H., JONKER, RENE T., VAN DOORN, PETER M., OZCETIN, H. KURTULUS
• Granted Patent: US 6,611,922 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43

Abstract

A time synchronization device and method for synchronizing an internal clock of the power monitor to a periodically stable frequency. Cycles of the periodically stable frequency are counted after each elapse of a predetermined time period. The elapse of the predetermined time period defines a present window and a previous window. A counting error and a change in counting error are calculated, wherein the change in counting error is the difference of a counting error calculated for the present window and a counting error calculated for the previous window. The present method detects when a change in counting error is within a predetermined range. When the counting error is within the predetermined range, the internal clock of the power monitor is adjusted to the line frequency according to the counting error calculated for the present window.

In another embodiment, a time of the internal clock is synchronized to a universal time, the time of the internal clock advancing at a predetermined rate. First, the present device and method receives a time synchronization message from an entity at a first free running counter count. The time synchronization message contains the universal time when the time synchronization message was sent. Thereafter, the time synchronization message is processed at a second free running counter count to determine the universal time. The time of the internal clock is compared to the universal time plus a processing time which is determined by the difference between the second free running counter count and the first free running counter count. Finally, the predetermined rate of advance of the internal clock is adjusted if the internal time differs from the universal time plus the processing time.

Claims

1. A time synchronization device of a power monitor for synchronizing a time of an internal clock to a line frequency, the internal time advancing at a predetermined rate, the device comprising:

a counter operative to count cycles of the line frequency after each elapse of a predetermined time period, said elapse of said predetermined time period defining a present window and a previous window;

a processor operative to calculate a counting error and a change in counting error, said change in counting error being the difference of a counting error calculated for said present window and a counting error calculated for said previous window;

wherein said processor detects when said change in counting error is within a predetermined range; and

adjusting means for adjusting the internal clock to the line frequency according to said counting error calculated for said present window when said change in counting error is within said predetermined range.

2. The device according to claim 2, wherein said adjusting means modifies the count of a decrement counter that keeps time for the internal clock.

3. A method for synchronizing a time of an internal clock to a periodically stable frequency which provides accurate time intervals, the method comprising the steps of:

counting cycles of the periodically stable frequency after each elapse of a predetermined time period, said elapse of said predetermined time period defining a present window and a previous window;

calculating a counting error and a change in counting error, said change in counting error being the difference of a counting error calculated for said present window and a counting error calculated for said previous window;

detecting when said change in counting error is within a predetermined range; and

adjusting the internal clock to the periodically stable frequency according to said counting error calculated for said present window, when said change in counting error is within said predetermined range.

4. The method according to claim 3, wherein said predetermined period is about 3600 seconds.

5. The method according to claim 3, wherein said predetermined range is about minus one to one.

6. The method according to claim 3, further comprising the steps of:

receiving a time synchronization message from an entity at a first free running counter count, said time synchronization message containing a universal time when the time synchronization message was sent;

processing said time synchronization message at a second free running counter count to determine said universal time.

7. The method according to claim 6, wherein said entity is a master computer.

8. The method according to claim 6, wherein said entity is a global positioning system.