Integrated radio frequency , optical, photonic, analog and digital functions in a semiconductor structure and method for fabricating semiconductor structure utilizing the formation of a compliant substrate for materials used to form the same

• US 20030015707A1
• Filed: 07/17/2001
• Published: 01/23/2003
• Est. Priority Date: 07/17/2001
• Status: Abandoned Application

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Farber, Bryan K., Escalera, Nestor Javier, Emrick, Rudy M., Franson, Steven James, Bosco, Bruce Allen
• Application Number:
  US09/905,869
• Publication Number:
  US 20030015707A1
• Time in Patent Office: Days
• US Class Current: 257/73
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Radio frequency, optical, logic and other circuits in both silicon and compound semiconductor materials may be combined and interconnected in a single semiconductor structure.

Claims

1. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate on a first side of the semiconductor structure;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

one or more silicon devices formed in the monocrystalline silicon substrate;

one or more compound semiconductor devices formed in the monocrystalline compound semiconductor material;

a metal layer interconnecting at least one compound semiconductor device and at least one silicon device on a surface of the first side of the semiconductor structure with reliable step coverage for the topography of the surface.

2. The semiconductor structure of claim 1 further comprising:

a metallic ground plane formed on a second side of the semiconductor structure.

3. The semiconductor structure of claim 2 wherein the metal layer forms a transmission line in association with the metallic ground plane.

4. The semiconductor structure of claim 1 further comprising

a metal via from the first side of the semiconductor structure to a second side of the semiconductor structure.

5. The semiconductor structure of claim 4 further comprising:

a metallic ground plane formed on the second side of the semiconductor structure, the metal via electrically contacting the metallic ground plane.

6. The semiconductor structure of claim 4 further comprising:

a second metal via from the first side of the semiconductor structure to the second side of the semiconductor structure; and

a second side metal layer formed on the second side of the semiconductor structure and including an interconnect portion electrically contacting both the metal via and the second metal via.

7. The semiconductor structure of claim 6 wherein the second side metal layer further comprises a ground plane portion.

8. The semiconductor structure of claim 7 further comprising:

second side insulation layer electrically insulating the interconnect portion and the ground plane portion of the second side metal layer.

9. The semiconductor structure of claim 1 further comprising:

a dielectric layer overlying the monocrystalline compound semiconductor material;

a monocrystalline semiconductor layer overlying the dielectric layer;

one or more semiconductor devices formed in the monocrystalline semiconductor layer; and

a metallic via extending through the dielectric layer.

10. The semiconductor structure of claim 9 wherein the metallic via forms an electrical connection between the metal layer and a semiconductor device formed in the monocrystalline semiconductor layer.

11. The semiconductor structure of claim 9 further comprising:

a second metal layer overlying the dielectric layer, the metallic via in electrical contact with a portion of the second metal layer.

12. The semiconductor structure of claim 11 wherein the metallic via forms an electrical connection between the metal layer and the second metal layer.

13. The semiconductor structure of claim 11 wherein the metallic via forms an electrical connection between a compound semiconductor device and the second metal layer.

14. The semiconductor structure of claim 9 further comprising:

ground plane metallization overlying the dielectric layer; and

a metallic via defined in the dielectric layer to electrically contact the ground plane metallization.

16. The semiconductor structure of claim 15 wherein the monocrystalline silicon substrate is doped to be conductive.

17. The semiconductor structure of claim 15 further comprising:

a metallic ground plane overlying the monocrystalline silicon substrate on a second side of the semiconductor structure.

19. The semiconductor structure of claim 18 wherein the light emitting device comprises a light emitting diode.

20. The semiconductor structure of claim 18 wherein the light emitting device comprises a laser.

21. The semiconductor structure of claim 20 wherein the light emitting device comprises a vertical cavity surface emitting laser.

22. The semiconductor structure of claim 20 wherein the light emitting device and the light detecting device are coplanar in the monocrystalline compound semiconductor material.

24. The semiconductor structure of claim 23 further comprising:

a light reflecting device positioned to reflect light from the compound semiconductor light emitting device to the silicon light detecting device.

26. The semiconductor structure of claim 25 further comprising:

a dielectric layer formed between the compound semiconductor light emitting device and the compound semiconductor light detecting device, the optical waveguide formed on the dielectric layer.

27. The semiconductor structure of claim 26 wherein the optical waveguide comprises:

a reflective first end proximate the compound semiconductor light emitting device; and

a reflective second end proximate the compound semiconductor light detecting device.

28. The semiconductor structure of claim 26 further comprising a silicon device formed in the monocrystalline silicon substrate.

29. The semiconductor structure of claim 28 wherein the silicon device comprises a modulator in electrical communication with the compound semiconductor light emitting device.

30. The semiconductor structure of claim 26 further comprising a compound semiconductor device formed in the monocrystalline compound semiconductor material.

31. The semiconductor structure of claim 28 wherein the compound semiconductor device comprises an amplifier in electrical communication with the compound semiconductor light detecting device.

15. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate on a first side of the semiconductor structure;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

one or more compound semiconductor devices formed in the monocrystalline compound semiconductor material;

metallization on the first side of the semiconductor structure; and

a via extending through the monocrystalline compound semiconductor material, the monocrystalline perovskite oxide material and the amorphous oxide material to form an electric plane probe in the monocrystalline silicon substrate.

18. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a compound semiconductor light emitting device; and

a compound semiconductor light detecting device conFIG.d to detect light emitted by the light emitting device, forming an optical interconnect of the semiconductor structure.

23. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a compound semiconductor light emitting device formed in the monocrystalline compound semiconductor material; and

a silicon light detecting device formed in the monocrystalline silicon substrate and conFIG.d to detect light emitted by the compound semiconductor light emitting device, forming an optical interconnect of the semiconductor structure.

25. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a compound semiconductor light emitting device formed in the monocrystalline compound semiconductor material;

a compound semiconductor light detecting device formed in the monocrystalline compound semiconductor material; and

an optical waveguide coupled with the compound semiconductor light emitting device and the compound semiconductor light detecting device, forming an optical interconnect.

32. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a bipolar transistor; and

a first transmission line electrically coupled with a base of the bipolar transistor; and

a second transmission line electrically coupled with a collector of the bipolar transistor.

33. The semiconductor structure of claim 32 wherein the bipolar transistor comprises a silicon bipolar junction transistor formed in the monocrystalline silicon substrate.

34. The semiconductor structure of claim 32 wherein the bipolar transistor comprises compound semiconductor heterojunction bipolar transistor formed in the monocrystalline compound semiconductor material.

36. The semiconductor structure of claim 35 further comprising:

an oscillator; and

a mixer coupled with the second transmission line and the oscillator.

37. The semiconductor structure of claim 36 further comprising:

a filter coupled to the mixer; and

an amplification circuit coupled with the filter.

38. The semiconductor structure of claim 37 wherein the oscillator and the mixer are formed from compound semiconductor devices.

39. The semiconductor structure of claim 38 wherein the filter and the amplification circuit are formed at least in part from silicon devices.

40. The semiconductor structure of claim 35 further comprising a control circuit coupled with the compound semiconductor transistor and formed at least in part from silicon devices.

35. A semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a compound semiconductor transistor formed in the monocrystalline compound semiconductor material;

a first transmission line feeding a gate of the compound semiconductor transistor; and

a second transmission line feed by a drain of the compound semiconductor transistor.

41. A semiconductor structure operable as an integrated down converter, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a compound semiconductor transistor conFIG.d to receive an input signal;

a compound semiconductor oscillator;

a compound semiconductor mixer having a first input coupled with the compound semiconductor transistor and a second input coupled with the a compound semiconductor oscillator and an output;

a filter having an input coupled to the output of the compound semiconductor mixer and an output;

an amplification circuit having an input coupled with the output of the filter; and

a control circuit for controlling operation as an integrated down converter.

42. The semiconductor structure of claim 41 further comprising:

a first transmission line coupled between an input of the integrated down converter and the compound semiconductor transistor; and

a second transmission line coupled between a drain of the compound semiconductor transistor and the compound semiconductor mixer.

43. The semiconductor structure of claim 41 wherein the control circuit comprises silicon devices integrated on the monocrystalline silicon substrate.

44. The semiconductor structure of claim 43 wherein the amplification circuit includes a control input coupled with the control circuit to receive a control signal.

45. The semiconductor structure of claim 41 wherein the compound semiconductor transistor is coupled with the control circuit to receive a bias signal.

46. The semiconductor structure of claim 45 wherein the control circuit comprises silicon devices formed on a silicon portion of the semiconductor structure.

48. The semiconductor structure of claim 47 further comprising a transmission line coupled between the photodiode and the first amplifier.

49. The semiconductor structure of claim 47 further comprising a transmission line coupled between the second amplifier and the output.

47. A semiconductor structure operable as a transimpedance amplifier, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a photodiode coupled with an input of the transimpedance amplifier and formed on a compound semiconductor portion of the semiconductor structure;

first and second amplifiers formed at least in part on a silicon portion of the semiconductor structure, the first amplifier coupled with the photodiode and the second amplifier coupled with an output of the transimpedance amplifier; and

a feedback resistor coupled from the output to the first amplifier.

50. A semiconductor structure operable as an integrated phase shifter, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a plurality of phased array channels, each phased array channel including

a compound semiconductor transistor conFIG.d to receive a channel

input signal, and

a phase shift element.

51. The integrated phase shifter of claim 50 wherein the phase shift element is formed on a silicon portion of the semiconductor structure.

52. The integrated phase shifter of claim 51 wherein the phase shift element is formed on the silicon substrate of the semiconductor structure.

53. The integrated phase shifter of claim 51 wherein the phase shift element is formed of epitaxial silicon formed on a part of the silicon substrate of the semiconductor structure.

54. The integrated phase shifter of claim 50 wherein the phase shift element comprises a micro-electromechanical system.

55. The integrated phase shifter of claim 50 wherein the phase shift element comprises a PIN diode.

56. The integrated phase shifter of claim 50 further comprising:

a control circuit coupled with each phased array channel plurality of phased array channels.

58. The semiconductor structure of claim 57 wherein the transmit/receive switch comprises a micro-electromechanical system.

59. The semiconductor structure of claim 57 further comprising a control circuit formed on a silicon portion of the semiconductor structure.

60. The semiconductor structure of claim 59 wherein the transmit/receive module comprises at least in part compound semiconductor devices formed in the monocrystalline compound semiconductor material.

57. A semiconductor structure operable as an integrated transceiver, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

a transmit/receive switch conFIG.d to be coupled with an antenna;

a transmit/receive module coupled with the transmit/receive switch; and

a radio frequency (RF) and intermediate frequency (IF) circuit coupled with the receive module.

61. A semiconductor structure operable as an optical line amplifier, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

an input optical waveguide;

an input optical waveguide;

a first multiplexer/demultiplexer coupled with the input optical waveguide;

a second multiplexer/demultiplexer coupled with the output optical waveguide; and

optical amplifiers bi-directionally coupled between the first multiplexer/demultiplexer and the second multiplexer/demultiplexer.

62. The semiconductor structure of claim 61 wherein the optical amplifiers comprise semiconductor optical amplifiers.

63. The semiconductor structure of claim 61 wherein the optical amplifiers comprise Raman amplifiers.

64. The semiconductor structure of claim 61 wherein the optical amplifiers comprise Erbium doped fiber amplifiers.

65. The semiconductor structure of claim 61 wherein the first multiplexer/demultiplexer and the second multiplexer/demultiplexer each comprise an arrayed waveguide grating multiplexer/demultiplexers.

66. A semiconductor structure operable as a transimpedance amplifier, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

an integrated optical waveguide conFIG.d to receive a composite optical signal including a plurality of individual optical signals;

an optical demultiplexer coupled with the integrated optical waveguide to separate the individual optical signals;

a plurality of photodetectors conFIG.d to convert the individual optical signals to individual electrical signals; and

an amplification circuit coupled with the plurality of photodetectors.

67. The semiconductor structure of claim 66 wherein the optical demultiplexer comprises an arrayed waveguide grating demultiplexer.

68. The semiconductor structure of claim 66 wherein the optical demultiplexer is formed at least in part of compound semiconductor devices on the monocrystalline compound semiconductor material.

69. The semiconductor structure of claim 68 wherein the amplifier circuit is formed at least in part of silicon devices of a silicon portion of the semiconductor structure.

70. The semiconductor structure of claim 68 wherein the amplifier circuit comprises a plurality of amplifiers, each amplifier operative to amplify a respective individual electrical signal.

71. The semiconductor structure of claim 68 wherein the photodiode is a silicon diode formed in a silicon portion of the semiconductor structure.

72. A semiconductor structure operable as an optical transceiver, the semiconductor structure comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material;

an optical to electrical converter circuit;

an electrical to optical converter circuit; and

a controller coupled with the optical to electrical converter circuit and the electrical to optical converter circuit.

73. The semiconductor structure of claim 72 wherein the optical to electrical converter circuit comprises:

a photodetector;

an amplification circuit coupled with the photodetector;

a clock and data recovery circuit coupled with the amplification circuit; and

a demultiplexer coupled with the clock and data recovery circuit.

74. The semiconductor structure of claim 72 wherein the electrical to optical converter circuit comprises:

a multiplexer;

a clock synchronization circuit coupled with the multiplexer;

a laser driver coupled with the clock synchronization circuit and the multiplexer; and

a laser diode coupled with the laser driver.

75. The semiconductor structure of claim 74 wherein the amplification circuit comprises:

a transimpedance amplifier; and

a limiting amplifier coupled in series with the transimpedance amplifier.