Channel equalization system and method
First Claim
1. A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising:
- a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal;
a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal;
a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal;
a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having;
a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal, a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and
a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.
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Accused Products
Abstract
A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities. A Unified Network Communication & Processor System or UniNet is a New generation network architecture of packet/circuit communication processors or Internet networking processor, that increases speeds over any communication channels and topologies, synchronizing, enabling, improving, controlling and securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data corn backbone. The present invention is capable of operating on any topology with distributed intelligence and data switching/routing, which is located at the edge. This method not only alleviates the ever increasing data processing bottleneck which is currently done by the data communication and telecom switch and routers, but it also enables new and next generation Internet Processor architecture. The UniNet is also a flexible solution for the novel concept that the capability of a network interface should depend on the level of service assigned to a service access point, not the capacity of the total network, such as transaction services with a short burst of messages with short access delay. The present invention increases channel capacity by using a parallel or multi-channel structure in such wireless and wireline at the edge or the core of. This new architecture of the present invention uses parallel bitstreams in a flexible way and distributed switching/routing technique, is not only to avoid the potential bottlenet of centralized switches, but also to increase speed with intelligence that is seamlessly integrating into the Fiber Optic Backbone such as WDM and SONET of the MAN/WAN network with a Real-time guarantees, different types of traffic (such as Stringent synchronous, isochronous, and asynchronous data messages) with different demands, and privacy & security of multi access and integrated services environment.
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Citations
12 Claims
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1. A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising:
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a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal;
a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal;
a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal;
a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having;
a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal, a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and
a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification