Integrated circuit die having an interference shield
First Claim
Patent Images
1. An integrated circuit package, comprising:
- an integrated circuit including a first circuit, and at least one second circuit, the first circuit being surrounded on lateral sides by a plurality of conductive vias; and
a package substrate having a ground plane, whereby the conductive vias and ground plane protect the second circuit from electromagnetic interference from the first circuit.
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Abstract
A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.
30 Citations
20 Claims
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1. An integrated circuit package, comprising:
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an integrated circuit including a first circuit, and at least one second circuit, the first circuit being surrounded on lateral sides by a plurality of conductive vias; and
a package substrate having a ground plane, whereby the conductive vias and ground plane protect the second circuit from electromagnetic interference from the first circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit for mounting onto a flip chip package, the integrated circuit comprising:
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a semiconductor substrate;
a plurality of metal layers; and
a plurality of conductive vias, wherein a first circuit is within a perimeter defined by the conductive vias and a second circuit is disposed outside of the perimeter, whereby the conductive vias provide electromagnetic shielding. - View Dependent Claims (11, 12, 13, 14, 15, 17, 18, 19, 20)
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16. A method of providing a Faraday cage for an integrated circuit die contained in a package, the method comprising:
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providing conductive vias about a periphery of a circuit in the integrated circuit die; and
mounting the integrated circuit die on a package substrate, the conductive vias being electrically coupled to a conductive plane of the package substrate.
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Specification