Address calculation unit for java or java-like native processor

• US 20030018879A1
• Filed: 05/10/2002
• Published: 01/23/2003
• Est. Priority Date: 05/10/2001
• Status: Active Grant

• Current Assignee: ZW Company LLC
• Original Assignee: ZW Company LLC
• Inventors: Ciambella, Gary, Sahraoui, Zohair
• Granted Patent: US 7,366,882 B2
• Time in Patent Office: Days
• US Class Current: 712/1
• CPC Class Codes: G06F 9/3555 using scaling, e.g. multiplication of index

Abstract

A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.

Claims

1. In an object-oriented language processor, an address calculation unit comprising:

one or more inputs for receiving a local variable pointer;

one or more inputs for receiving a local variable number;

a scaling portion for scaling the local variable number; and

a generating portion for generating memory addresses for elements contained in one or more object oriented data structures by using the scaled local variable number, wherein the generating portion generates the memory addresses in a single processor clock-cycle.

2. The address calculation unit of claim 1 further comprising a memory, wherein the memory contains one or more base address.

3. The address calculation unit of claim 2, wherein the base addresses are the base addresses of the object oriented data structures.

4. An object oriented processor comprising:

an ACU, the ACU comprising a generating portion for generating memory addresses for elements contained in object oriented data structures, wherein

the generating portion generates the addresses in a single clock-cycle.

5. The object oriented processor of claim 4, wherein the ACU comprises a circuit, the circuit for providing one or more object oriented data structure offsets to the ACU.

6. The object oriented processor of claim 5, wherein the data structure offsets comprise offsets for data structures used by the object oriented processor.

7. The object oriented processor of claim 6, wherein the processor comprises a Java native processor.

8. The object oriented process of claim 4, wherein the processor further comprises an ALU.

9. A method of calculating addresses in an object-oriented processor, the method comprising:

a. receiving a base value;

b. receiving an index;

c. scaling the index to produce a scaled index; and

d. adding the scaled index to the base value to generate an address, wherein steps a. to d. are accomplished in a single clock cycle of the processor.

10. In an object oriented processor, a base address register comprising:

a register for holding the base address of an object.

11. The processor of claim 10, wherein the object-oriented processor comprises a Java processor.

12. The processor of claim 10, further comprising an address calculation unit, wherein the register is coupled to the address calculation unit via a dedicated connection.

13. The processor of claim 12, wherein the address calculation unit further comprises a circuit, the circuit for providing one or more object oriented data structure offsets to the address calculation unit, and wherein the address calculation unit generates memory addresses for elements contained in the one or more object oriented data structures in a single processor clock-cycle.

16. The processor of claim 15, wherein the arguments comprise absolute addresses for the data structures, and a control word.

17. The processor of claim 16, wherein the control word can specify an operation, a scaling factor, and an offset.

18. The processor of claim 15, wherein the ACU comprises a control for receiving inputs from one or more processor hardware blocks to generate addresses for elements of the object oriented data structures.

19. The processor of claim 18, wherein the addresses are generated in one processor clock cycle.

20. The processor of claim 15, further comprising a separate ALU.

14. A processor including an ACU, the ACU comprising:

a. a circuit for receiving a control word from the processor,

b. a circuit for receiving a stack pointer, a local variable pointer, and a base address;

c. an adder circuit;

d. a selecting circuit for selecting one of the stack pointer, local variable pointer and base address, the selecting circuit producing an output comprising the selection, the output coupled to the adder;

e. a circuit for receiving a local variable number; and

f. a circuit for shifting the local variable number, coupled to the circuit for receiving a local variable number, the circuit for shifting producing a shifted local variable number output, the output coupled to a second port of the adder.

15. A processor comprising:

an ACU, the ACU comprising inputs for receiving arguments that reference object oriented data structures.