Semiconductor package

• US 20030020171A1
• Filed: 07/23/2002
• Published: 01/30/2003
• Est. Priority Date: 07/27/2001
• Status: Abandoned Application

• Current Assignee: Nokia Corporation
• Original Assignee: Nokia Corporation
• Inventors: Dutta, Amit, Yoshimura, Makoto, Fujii, Takaharu, Iwamoto, Takashi
• Application Number:
  US10/201,360
• Publication Number:
  US 20030020171A1
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor package is provided which enables various interconnections between pins at a low cost. In an embodiment of the invention, the semiconductor package has a base substrate and a group of IC'"'"'s (spacer IC'"'"'s, routing IC'"'"'s, and flip chip IC'"'"'s) stacked on the base substrate in three dimensions. The routing IC is an interposer for wiring between the pins of the chips located above and below the routing IC and enables the integration of passive elements.

Claims

1. A semiconductor package comprising:

one or more of the group consisting of;

routing IC'"'"'s, flip chip IC'"'"'s, and spacers; and

a base substrate,

wherein one or more of said IC'"'"'s and spacers are stacked in three dimensions on the base substrate of the semiconductor package, and said routing IC comprises electric means for wiring respectively the top and bottom surfaces of said routing IC, said routing IC having through holes for connecting with the routing IC'"'"'s adjacent layers or the base substrate.

2. The semiconductor package of claim 1, wherein said routing IC comprises one or more passive elements.

3. The semiconductor package of claim 1, wherein said routing IC comprises one or more active elements.

4. The semiconductor package of claim 2, wherein said routing IC comprises one or more active elements.

5. The semiconductor package of claim 1, wherein said routing IC'"'"'s differ from each other in at least one of the group comprising the numbers of said through holes, said active elements, said passive elements provided, and in the area occupied by the active and passive elements.

6. The semiconductor package of claim 4, wherein said routing IC'"'"'s differ from each other in at least one of the group comprising the numbers of said through holes, said active elements, said passive elements provided, and in the area occupied by the active and passive elements.

7. The semiconductor package of claim 1, further comprising an electric means for changing the routing of said routing IC'"'"'s.

8. The semiconductor package of claim 6, further comprising an electric means for changing the routing of said routing IC'"'"'s.

9. The semiconductor package of claim 1, further comprising an electric means for changing the construction of at least one of the passive elements and active elements, which are placed on the routing of said routing IC.

10. The semiconductor package of claim 9, further comprising an electric means for changing the construction of at least one of the passive elements and active elements, which are placed on the routing of said routing IC.

11. The semiconductor package of claim 1, wherein bonding between the individual layers is performed by solder balls or a conductive adhesive.

12. The semiconductor package of claim 10, wherein bonding between the individual layers is performed by solder balls or a conductive adhesive.