System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system
First Claim
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1. A system comprising:
- a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;
a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;
a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;
wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM.
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Abstract
A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.
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Citations
18 Claims
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1. A system comprising:
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a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;
a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;
a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;
wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13)
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14. A method of in-system programming of EEPROMs, the EEPROMS being coupled to provide configuration code to FPGAs, comprising:
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transferring at least portions of a configuration code file to a system management processor of the system;
providing a system management bus coupling the system management processor to common configuration logic, the common configuration logic coupled to a plurality of serial busses coupled to a plurality of the EEPROMS;
setting selection logic to designate an active serial bus coupled to an EEPROM to be programmed;
verifying compatibility of the configuration code file with the active serial bus;
erasing at least a portion of the EEPROM to be programmed;
writing at least a portion of the configuration code file from the system management processor, over the system management bus, over the active serial bus, and into the EEPROM; and
causing configuration code to be loaded from the EEPROM into at least one FPGA. - View Dependent Claims (15, 16, 17)
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18. A method of self-repairing a system by in-system programming of EEPROMs, the EEPROMS being coupled to provide configuration code to FPGAs, comprising:
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detecting an error in FPGA configuration code as the FPGA configuration code is fetched from an EEPROM;
locating an FPGA configuration code file in a database;
transferring at least portions of the configuration code file to a system management processor of the system;
providing a system management bus coupling the system management processor to common configuration logic, the common configuration logic being coupled to a plurality of serial busses coupled to a plurality of the EEPROMS;
setting selection logic to designate an active serial bus coupled to an EEPROM to be programmed;
verifying compatibility of the configuration code file with the active serial bus;
erasing at least a portion of the EEPROM to be programmed;
writing at least a portion of the configuration code file from the system management processor, over the system management bus, over the active serial bus, and into the EEPROM; and
causing configuration code to be loaded from the EEPROM into at least one FPGA.
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Specification