Compact analog-multiplexed global sense amplifier for rams
First Claim
1. A RAM having a plurality of local bit lines and a plurality of global bit lines comprising:
- means for coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines;
means for selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines for a write operation; and
means for coupling non-selected global bit lines to a vdd signal.
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Abstract
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers).
In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. The global bit line pairs with no voltage development generate zero voltage development on the local bit lines and the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.
9 Citations
17 Claims
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1. A RAM having a plurality of local bit lines and a plurality of global bit lines comprising:
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means for coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines;
means for selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines for a write operation; and
means for coupling non-selected global bit lines to a vdd signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for writing data to a RAM having a plurality of local bit lines and a plurality of global bit lines comprising:
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coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines;
selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines during the writing data; and
means for coupling non-selected global bit lines to a vdd signal during the writing data. - View Dependent Claims (10, 11, 12)
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13. A RAM with differential local sensing means comprising:
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an odd block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective odd bit line;
an even block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective even bit line; and
a plurality of local sense amplifiers positioned between the odd block of data cells and the even block of data cells, wherein each local sense amplifier of the plurality of local sense amplifiers is shared by a respective odd bit line, a respective even bit line, and a respective global bit line, and comprises of;
four transistors configured as two cross-coupled latches having a first output and a second output;
a first gate transistor for coupling the first output of the two cross-coupled latches to the respective global bit line; and
a second gate transistor for coupling the second output of the two cross-coupled latches to a complement signal of the respective global bit line. - View Dependent Claims (14, 15, 16, 17)
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Specification