Fingerprint biometric capture device and method with integrated on-chip data buffering

• US 20030021495A1
• Filed: 03/13/2002
• Published: 01/30/2003
• Est. Priority Date: 07/12/2001
• Status: Abandoned Application

• Current Assignee: Atrua Technologies Incorporated (Apple Inc.)
• Original Assignee: Atrua Technologies Incorporated (Apple Inc.)
• Inventors: Cheng, Ericson
• Application Number:
  US10/099,558
• Publication Number:
  US 20030021495A1
• Time in Patent Office: Days
• US Class Current: 382/312
• CPC Class Codes: G06Q 10/02 Reservations, e.g. for tickets, services or events
• CPC Class Codes: G06Q 20/04 Payment circuits
• CPC Class Codes: G06Q 20/4016 involving fraud or risk level assessment in transaction processing
• CPC Class Codes: G06Q 30/06 Buying, selling or leasing transactions
• CPC Class Codes: G06V 40/13 Sensors therefor
• CPC Class Codes: G07C 9/37 using biometric data, e.g. fingerprints, iris scans or voice recognition

Abstract

Invention provides a fingerprint biometric capture sensor device and method for capturing and either reconstructing fingerprint image or information concerning fingerprint without actually performing fingerprint image reconstruction. In another aspect, fingerprint biometric capture sensor device is integrated with on-chip data buffering. In another aspect, sensor device is integrated with on-chip processor. In another aspect, invention provides a fingertip sensor system including: fingertip sensor device generating analog first electrical signal representing feature of fingertip in response to placing fingertip in proximity with sensor device; analog-to-digital converter coupled with and receiving analog first electrical signal from sensor device and converting first electrical signal to a digital second electrical signal; at least one buffer coupled with and receiving digital second electrical signal from analog-to-digital converter and storing information corresponding to at least a portion of digital second electrical signal therein; and logic controlling operation of sensor, analog-to-digital converter, buffer, and host interface circuit.

Claims

1. A fingertip sensor system comprising:

a fingertip sensor device generating an analog first electrical signal representing a feature of said fingertip in response to placing said fingertip in proximity with said sensor device;

an analog-to-digital converter coupled with and receiving said analog first electrical signal from said sensor device and converting said first electrical signal to a digital second electrical signal;

at least one buffer coupled with and receiving said digital second electrical signal from said analog-to-digital converter and storing information corresponding to at least a portion of said digital second electrical signal therein; and

logic controlling operation of said sensor, said analog-to-digital converter, said buffer, and said host interface circuit.

2. The system in claim 1, wherein said system further comprising:

an input/output port for communicating with an external device; and

a host interface circuit coupled between said buffer and said input/output port to retrieve said stored information from said buffer and communicate a digital electrical signal to said external device via said input/output port.

3. The system in claim 2, wherein said external device comprises a host.

4. The system in claim 3, wherein said host comprises a processor.

5. The system in claim 1, wherein said buffer stores said information only transiently.

6. The system in claim 1, wherein said buffer comprises a frame buffer.

7. The system in claim 1, wherein said sensor device and said buffer are formed on a single common integrated circuit substrate.

8. The system in claim 2, wherein said sensor device, said analog-to-digital converter, said logic, said host interface circuit, and said buffer are formed on a single common integrated circuit substrate.

9. The system in claim 2, wherein said buffer receives a control signal from control logic at a control input port, and further comprises a write address decoder receiving a write memory address at a write-address input port, a read address decoder receiving a read memory address at a read-address input port, and a memory array receiving first data at a memory array input port and communicating second data at a memory array output port.

10. The system in claim 7, wherein said integrated circuit substrate comprises silicon.

11. The system in claim 7, wherein said integrated circuit substrate comprises gallium arsenide.

12. The system in claim 7, wherein said integrated circuit substrate comprises a semi-conducting material.

13. The system in claim 1, wherein said sensor device comprises a fingertip placement sensor device.

14. The system in claim 1, wherein said sensor device comprises a fingertip swipe sensor device.

15. The system in claim 1, wherein said at least one buffer comprises a single buffer.

16. The system in claim 1, wherein said at least one buffer comprises a plurality of buffers.

17. The system in claim 2, wherein said at least one buffer comprises a plurality of frame buffers.

18. The system in claim 2, wherein said sensor device comprises a fingertip placement sensor device and said buffer includes a memory array for storing a two-dimensional array of digitized samples extracted from said placement sensor device.

19. The system in claim 2, wherein said sensor device comprises a fingertip swipe sensor device and said buffer includes a memory array for storing a one-dimensional array of digitized samples extracted from said fingertip swipe sensor device.

20. The system in claim 10, wherein said sensor device comprises a sensor transducer array, at least one control signal input port, and at least one sensor transducer array output port for communicating at least one output signal representing a characteristic of the sensed fingertip.

21. The system in claim 10, wherein said at least at least one sensor transducer array output port comprises a plurality of sensor transducer array output ports.

22. The system in claim 10, wherein said transducer array comprises a first plurality of transducer elements and said at least one output port comprises a second plurality of sensor transducer array output ports.

23. The system in claim 20, wherein said sensor device sensor array comprises an m-row×

n-column array of transducers.

24. The system in claim 9, wherein for said sensor device and said control inputs are coupled with said control logic.

25. The system in claim 21, wherein said transducer outputs provide input analog signals to said analog-to-digital converter.

26. The system in claim 1, wherein said analog-to-digital converter comprises at least one control input, at least one analog input port 8, and at least one digital output port.

27. The system in claim 26 wherein said at least one control input connects to said control logic.

28. The system in claim 1, wherein said sensor device generates u-analog outputs and communicates said u-analog outputs to said analog-to-digital converter.

29. The system in claim 1, wherein said analog-to-digital converter generates a digital output signal at the analog-to-digital converter output port from a received sensor analog input signal at an input port.

30. The system in claim 29, wherein said digital output signal comprises a v×

p-bits wide digital output signal.

31. The system in claim 30, wherein said buffer memory array is a two dimensional memory array of size h×

m×

n×

p-bits, where h is the number of frames the buffer can store, m is the number of rows in the sensor array, n is the number of columns in the sensor array, and p is the data width of the digitized value of a single sensor device array transducer element.

32. The system in claim 31, wherein said data input port of the buffer comprises a v×

p-bits wide data input port.

33. The system in claim 32, wherein said data input port connects the output of the analog-to-digital converter to the memory array.

34. The system in claim 33, wherein the width of said data input port is sized to match the output data width of the analog-to-digital converter.

35. The system in claim 34, wherein data is written into the memory array via a data input port.

36. The system in claim 35, wherein said memory array receives data as fast as the analog-to-digital converter generates the data.

37. The system in claim 36, wherein said data output port of the buffer is q-bits wide and connects the memory array to the host interface block.

38. The system in claim 37, wherein data is read from the memory array via the data output port.

39. The system in claim 38, wherein said memory array is dual-ported to allow simultaneously writes by the A/D converter and reads by the host interface.

40. The system in claim 39, wherein said memory array includes a write-address input port receiving a write address signal from said control block and feeds the write-address decoder, which decodes the address to select a memory array block within the memory array to be loaded from the A/D converter through the data input port.

41. The system in claim 40, wherein said memory array block is single element of size p-bits.

42. The system in claim 40, wherein said memory array block comprises multiple elements.

43. The system in claim 40, wherein said memory array block comprises multiple elements each having p-bits.

44. The system in claim 9, wherein said control logic generates write-enable signals that strobe the data from the analog-to-digital converter into the selected memory array block.

45. The system in claim 44, wherein said write-enable signals are part of the control input port.

46. The system in claim 40, wherein said memory array includes a read-address input port receiving a read address from the control block and feeds the read-address decoder, which decodes the address to select a block within the memory array to be read via the data output port.

47. The system in claim 46, wherein the memory array block is a single element of size q-bits.

48. The system in claim 46, wherein the memory array block comprises a multiple of q-bits.

49. The system in claim 46, wherein control logic generates read-enable signals, which are part of the control input port and enable the selected memory array block to drive the data output port.

50. The system in claim 49, wherein said control logic block comprises a sensor control, an analog-to-digital converter control, an interval timer, a buffer write control, and a buffer read control.

51. The system in claim 50, wherein said sensor control generates addresses and control inputs to the sensor.

52. The system in claim 51 wherein said sensor control further connects to the analog-to-digital converter control.

53. The system in claim 52, wherein said analog-to-digital converter control generates controls signals into the analog-to-digital converter and the sensor array control necessary to digitize a frame of data.

54. The system in claim 53, wherein the analog-to-digital converter will run until a frame of data is loaded into the buffer.

55. The system in claim 50, wherein said interval timer is used to trigger the A/D conversion of the next frame.

56. The system in claim 55, wherein said interval timer provides timing signals for the capture frames at a uniform rate and for the automatic switchover and automatic filling of additional frame buffers without host intervention.

57. The system in claim 56, wherein said ability to automatically fill the frame buffers at some set interval permits efficient use of multiple frame buffers.

58. The system in claim 50, wherein said buffer write control generates write addresses and write strobes.

59. The system in claim 58, wherein said write addresses feed the write-address decoder of the buffer.

60. The system in claim 58, wherein said write strobes are inputs into the memory array and cause output of the A/D converter to be loaded into the selected memory block.

61. The system in claim 58, wherein said buffer write control sequentially fills the memory array from the analog-to-digital converter.

62. The system in claim 61, wherein said write addresses reset to the beginning of the memory array when the end of the memory array is reached.

63. The system in claim 62, wherein loading of the memory array pauses if the memory array is full.

64. The system in claim 50, wherein said buffer read control generates read addresses and read strobes.

65. The system in claim 64, wherein said read addresses feed the read-address decoder of the buffer.

66. The system in claim 65, wherein said read strobes are inputs into the memory array and enable the outputs of the selected memory block to drive the output port of the memory array.

67. The system in claim 50, wherein said read control sequentially empties the memory array into the host interface.

68. The system in claim 65, wherein said read addresses reset to the beginning of the array when the end of the memory array is reached.

69. The system in claim 68, wherein the reading of the memory array will pause if the memory array is empty.

70. The system in claim 2, wherein said host interface includes an input port, a bi-directional I/O port, and control signals.

71. The system in claim 2, wherein said host interface responsibility includes converting between the internal logic format and the interface to the external host processor.

72. The system in claim 2, wherein said host interface generates requests to the buffer read control block in response to the host processor read access via the bi-directional I/O port.

73. The system in claim 70, wherein said input port comprises q-bits wide and receives data from the output of the buffer.

74. The system in claim 73, wherein said data output from said buffer is formatted by a data translation block into the appropriate output format for said bi-directional I/O port which provides an interface to the host processor.

75. The system in claim 74, wherein said bi-directional I/O port is implemented as an 8-bit parallel interface.

76. The system in claim 74, wherein said bi-directional I/O port is implemented as a Universal Serial Bus.

77. The system in claim 74, wherein said bi-directional I/O port is implemented as a serial peripheral interface.

78. A communication device comprising:

a fingerprint biometric sensor system for determining and authenticating an identity of a user of said communication device;

a transmitter for transmitting a first data including identity data for said user;

a receiver for receiving second data;

said fingerprint biometric sensor system including;

a fingertip sensor device generating an analog first electrical signal representing a feature of said fingertip in response to placing said fingertip in proximity with said sensor device;

an analog-to-digital converter coupled with and receiving said analog first electrical signal from said sensor device and converting said first electrical signal to a digital second electrical signal;

at least one buffer coupled with and receiving said digital second electrical signal from said analog-to-digital converter and storing information corresponding to at least a portion of said digital second electrical signal therein; and

logic controlling operation of said sensor, said analog-to-digital converter, said buffer, and said host interface circuit.

79. The communication device in claim 78, wherein said fingerprint biometric sensor system further comprising:

an input/output port for communicating with an external device; and

a host interface circuit coupled between said buffer and said input/output port to retrieve said stored information from said buffer and communicate a third digital electrical signal to said external device via said input/output port.

80. A method for reducing power consumption of a fingerprint capture device, said method comprising:

forming a fingerprint sensor on a first substrate;

forming device control and signal processing circuits for generating and converting an analog sensor signal carrying fingerprint information to a digital signal on said same first substrate, said signal processing circuits including an analog-to-digital converter; and

forming a buffer memory on said same first substrate, said buffer memory including a plurality of input ports selected to match a bit-width of an analog-to-digital converter.

81. A method for reducing power consumption of a fingerprint capture device, said method comprising:

powering a fingerprint sensor disposed on a first substrate to generate an analog detected signal in response to an externally applied fingerprint stimulus;

receiving said detected signal and processing said detected signal within processing circuits formed on said first substrate to generate an v×

p-bit digital signal carrying fingerprint information; and

storing said n-bit fingerprint information in a buffer memory disposed on said first substrate, said buffer memory including a number n of input ports to match said v-bit×

p-bit width of said v-bit×

p-bit digital fingerprint signal;

said powering, generating, receiving, and storing on said common first substrate and said matching of said v×

p-bit widths reducing power consumption of said device relative to devices having an external buffer on a substrate other than said first substrate.

82. The method for reducing power consumption of a fingerprint capture device in claim 81, further comprising:

reading said stored q-bit fingerprint information from said buffer and communicating said q-bit fingerprint information to an external device via an interface disposed on said first substrate.