Intermediate language accelerator chip

• US 20030023958A1
• Filed: 06/27/2002
• Published: 01/30/2003
• Est. Priority Date: 07/17/2001
• Status: Abandoned Application

• Current Assignee: Nazomi Communications Incorporated
• Original Assignee: Nazomi Communications Incorporated
• Inventors: Hillman, Dan, Patel, Mukesh K., Shiell, Jon, Kamdar, Jay, Raval, Udaykumar R.
• Application Number:
  US10/187,858
• Publication Number:
  US 20030023958A1
• Time in Patent Office: Days
• US Class Current: 717/146
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Claims

1. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an accelerator chip, the accelerator chip operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory, the accelerator chip being adapted to run at least portions of programs in an intermediate language.

2. The system of claim 1 wherein the programs in an intermediate language instructions are Java bytecodes.

3. The system of claim 2 wherein the processor runs a modified Java virtual machine.

4. The system of claim 1 wherein the intermediate language is in bytecode form.

5. The system of claim 1 wherein the accelerator chip is positioned on a memory bus.

6. The system of claim 1 wherein the memory comprises a number of memory units.

7. The system of claim 6 wherein the memory units include a static random access memory.

8. The system of claim 6 wherein the memory units include a flash memory.

9. The system of claim 1 wherein the processor runs a modified virtual machine.

10. The system of claim 1 wherein the accelerator chip does not run certain bytecodes but instead has a callback to the virtual machine running on the processor chip.

11. The system of claim 1 wherein the accelerator chip has a sleep mode with low power consumption.

12. The system of claim 1 wherein the processor chip is a system on a chip.

13. The system of claim 1 wherein the accelerator chip includes a hardware translator unit adapted to convert intermediate language instructions into native instructions and an execution unit adapted to execute the native instructions provided by the hardware translator unit.

14. The system of claim 13 wherein the hardware translator unit is adapted to convert Java bytecodes into native instructions.

15. The system of claim 1 wherein the accelerator chip includes an interface adapted to allow memory access for the accelerator chip to at least one memory, and to allow for access for the processor chip to the at least one memory.

16. The system of claim 15 wherein the interface comprises a first interface to the processor chip and a second interface to the memory unit, the second and first interface adapted to operate independently.

17. The system of claim 1 wherein the accelerator chip includes an instruction cache operably connected to store instructions to be executed within the accelerator chip.

18. The system of claim 17 wherein the accelerator chip includes an instruction cache operably connected to store instructions to be executed within the accelerator chip.

19. The system of claim 1 wherein the accelerator chip includes a hardware translator unit and a dedicated execution unit adapted to execute native instructions provided by the hardware translator unit, the dedicated execution engine only executing instructions provided by the hardware translator unit.

20. The system of claim 1 wherein the accelerator chip is integrated as a chip stack with the processor chip.

21. The system of claim 1 wherein the accelerator chip is on the same silicon as the memory.

22. The system of claim 1 wherein the accelerator chip is integrated as a chip stack with the memory.

23. The system of claim 1 wherein the processor chip is a system on a chip.

24. The system of claim 23 wherein the system on a chip is adapted for use in cellular phones.

25. The system of claim 1 wherein the accelerator chip supports execution of two or more intermediate languages.

26. The system of claim 25 wherein the intermediate languages are Java bytecodes and MSIL for C#/.NET.

27. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

a accelerator chip, the accelerator chip operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory, the accelerator chip being adapted to run at least portions of programs in an intermediate language, the hardware accelerator including a hardware translator unit adapted to covert intermediate language instructions into native instructions, and an execution engine adapted to execute the native instructions provided by the hardware translator unit.

28. The system of claim 27 wherein the programs in an intermediate instruction language are Java programs and the hardware translator unit coverts Java bytecodes into native instructions.

29. The system of claim 28 wherein the processor runs a modified Java virtual machine.

30. The system of claim 27 wherein the accelerator chip is positioned on a memory bus in between the processor chip and the at least one memory.

31. The system of claim 27 wherein the memory comprises a number of memory units.

32. The system of claim 31 wherein one of the memory units comprises a static random access memory.

33. The system of claim 31 wherein at least one of the memory units comprises a flash memory.

34. The system of claim 27 wherein the processor runs a modified virtual machine.

35. The system of claim 34 wherein the accelerator chip does not execute certain intermediate language instructions and a callback occurs when these intermediate language instructions occur, these intermediate language instructions being executed on the modified virtual machine running on the processor chip.

36. The system of claim 27 wherein the accelerator chip has a sleep mode with low power consumption.

37. The system of claim 27 wherein the processor chip is a system on a chip.

38. The system of claim 27 wherein the accelerator chip includes an interface adapted to allow for memory access for the accelerator chip to at least one memory, and to allow for memory access for the processor chip to the at least one memory.

39. The system of claim 27 wherein the accelerator chip further includes an instruction cache operably connected to the hardware translator unit storing the intermediate language instructions to be converted.

40. The system of claim 27 wherein the execution engine is a dedicated execution engine only executing instructions provided by the hardware translator unit.

41. An accelerator chip comprising:

a unit adapted to execute intermediate language instructions; and

an interface, the interface adapted to allow for memory access for the accelerator chip to at least one memory and to allow for memory access for a separate processor chip to the at least one memory.

42. The accelerator chip of claim 41 wherein the intermediate language instructions are Java bytecodes.

43. The accelerator chip of claim 41 wherein the accelerator chip does not execute certain intermediate language instructions but instead causes a callback to the separate processor chip.

44. The accelerator chip of claim 41 wherein the accelerator chip has a sleep mode with low power consumption.

45. The accelerator chip of claim 41 wherein the accelerator chip includes an instruction cache operably connected to operably connected to the hardware translator unit storing intermediate language instructions to be converted.

46. The accelerator chip of claim 41 wherein the unit includes a hardware translator unit adapted to convert intermediate language instructions into native instructions and an execution engine adapted to execute native instructions provided by the hardware translator unit.

47. The accelerator chip of claim 41 wherein the unit comprises a dedicated processor whose native instruction is the intermediate language instruction.

55. The accelerator chip of claim 47 wherein the intermediate language instructions are Java bytecodes.

48. An accelerator chip comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions;

an execution engine adapted to execute the native instructions provided by the hardware translator unit; and

an interface, the interface adapted to allow for memory access for the accelerator chip to at least one memory and to allow for memory access for a separate processor chip to the at least one memory.

49. The accelerator chip of claim 48 wherein the intermediate language instructions are Java bytecodes.

50. The accelerator chip of claim 48 wherein the accelerator chip does not execute every intermediate language instruction but some intermediate language instructions cause a callback to the separate processor chip running a modified virtual machine.

51. The accelerator chip of claim 48 wherein the accelerator chip has a sleep mode with low power consumption.

52. The accelerator chip of claim 48 wherein the accelerator chip further includes an instruction cache operably connected to the hardware translator unit storing intermediate language instructions to be converted.

53. The accelerator chip of claim 48 wherein the execution engine is a dedicated execution engine only executing instructions provided by the hardware translator unit.

54. An accelerator chip comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions;

an instruction cache operably connected to the hardware translator unit storing intermediate language instructions to be converted;

an execution engine adapted to execute the native instructions provided by the hardware translator unit; and

an interface, the interface adapted to allow for memory access for the accelerator chip to at least one memory and to allow for memory access for a separate processor chip to the at least one memory.

56. The accelerator chip of claim 54 wherein the accelerator chip does not execute every intermediate language instruction but for some intermediate language instructions causes a callback to a processor running a modified virtual machine.

57. The accelerator chip of claim 54 wherein the accelerator chip has a sleep mode with low power consumption.

58. The accelerator chip of claim 54 wherein the execution engine is a dedicated execution engine adapted to only execute instructions provided by the hardware translator unit.

59. An accelerator chip comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions; and

a dedicated execution engine adapted to execute the native instructions provided by the hardware translator unit, the dedicated execution engine only executing instructions provided by the hardware translator unit, wherein the hardware translator unit, rather than the execution engine, determines the address of the next intermediate language instruction to translate and provide to the dedicated execution engine.

60. The accelerator chip of claim 59 wherein the intermediate language instructions are Java bytecodes.

61. The accelerator chip of claim 59 wherein the accelerator chip does not execute every intermediate language instruction but some intermediate language instructions cause a callback to a separate processor chip running a modified virtual machine for interpretation.

62. The accelerator chip of claim 59 wherein the accelerator chip includes a sleep mode with low power consumption.

63. The accelerator chip of claim 59 wherein the accelerator chip includes an interface adapted to allow for memory access for the accelerator chip to at least one memory and allow for memory access for a separate processor chip to the at least one memory.

64. The accelerator chip of claim 59 wherein the accelerator chip further includes an instruction cache operably connected to the hardware translator unit storing intermediate language instructions to be converted.

65. A method of operating an accelerator chip comprising:

in a hardware translator unit, calculating the address of intermediate language instructions to execute;

obtaining the intermediate language instructions from a memory;

in the hardware translator unit, converting the intermediate language instructions to native instructions;

providing the native instructions to an execution engine; and

in the execution engine, executing the native instructions, wherein for at least one intermediate language instruction a callback to a separate processor chip running a virtual machine is done to handle the intermediate language instruction.

66. The method of claim 65 wherein the intermediate language instructions are Java bytecodes.

67. An accelerator chip comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions;

an execution engine adapted to execute the native instructions provided by the hardware translator unit;

an interface, the interface adapted to allow for memory access for the accelerator chip to at least one memory and to allow for memory access for a separate processor chip to the at least one memory; and

a graphics acceleration engine adapted to be interconnected to a display, the graphics acceleration engine executing intermediate language instructions concerning a display.

68. The accelerator chip of claim 67 wherein the intermediate language instructions are Java bytecodes.

69. The accelerator chip of claim 68 wherein Java based libraries are used.

70. The system of claim 69 wherein the Java based libraries include Java based programs.

71. The system of claim 70 wherein the Java based programs are modified Java programs.

72. The accelerator chip of claim 67 in which the display is an LCD display and the graphics acceleration engine implements an LCD display.

73. The accelerator chip of claim 72 wherein the graphics acceleration engine implements a Java LCD display library function.

74. A system comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions; and

an execution engine adapted to execute the native instructions provided by the hardware translator unit, the execution engine including at least one indexed instruction to do an indexed load from or store into an array, the instruction concurrently checking a first register storing an array pointer to see whether it is null.

75. The system of claim 74 wherein the hardware translator unit and the execution engine are positioned on an accelerator chip.

76. The system of claim 74 wherein the accelerator chip is positioned between a processor chip and a memory.

77. The system of claim 74 wherein the intermediate language instructions are Java instructions.

78. The system of claim 74 wherein the hardware translator unit translates some array loading and array storing instructions so as to use at least one index instruction.

79. A system comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions; and

an execution engine adapted to execute the native instructions provided by the hardware translator unit, the execution engine including at least one indexed instruction to do an indexed load from or store into an array, the execution engine having a zero checking unit adapted to check whether a first register storing an array pointer to see whether it is null, the null checking unit of the execution engine working concurrently with portions of the execution engine doing the indexed load from or store into an array.

80. The system of claim 79 in which the intermediate language instructions are Java bytecodes.

81. The system of claim 79 in which the hardware translator unit and execution engine are on an accelerator chip.

82. An system comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions; and

an execution engine adapted to execute the native instructions provided by the hardware translator unit, the execution engine including at least one bounds checking instruction, the bounds checking instruction ensuring that an index value stored in a first register is less than or equal to an array length value stored in a second register.

83. The system of claim 82 wherein the intermediate language instructions are Java bytecodes.

84. The system of claim 82 in which the hardware translator unit and execution engine are part of an accelerator chip.

85. The system of claim 84 in which the accelerator chip is positioned between a processor chip and a memory.

86. An system comprising:

a hardware translator unit adapted to covert intermediate language instructions into native instructions; and

an execution engine adapted to execute the native instructions provided by the hardware translator unit, the execution engine including an instruction that based on values from the last addition or subtraction stores an 1, 0, or −

1 in a register.

87. The system of claim 86 wherein the values include the N, Z and carry bits.

88. The system of claim 86 wherein the signed instruction checks the Z and the N bits. If the Z bit is high, a 0 is put in the register. If the Z bit is low and N is low, 1 is put in the register. If the Z bit is low and N is high, a −

1 is put in the register.

89. The system of claim 86 in which an unsigned instruction check is done to check the Z and C bits. If the Z bit is high, a 0 is put in the register. If the Z bit is low, and C is high, 1 is put in the register. If the Z bit is low and the C is low, −

1 is put in the register.

90. The system of claim 86 in which both signed and unsigned checks are done.

91. The system of claim 86 wherein the hardware translator unit and execution engine are on an accelerator chip.

92. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an accelerator chip, the accelerator chip operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory, the accelerator chip being adapted to run at least portions of programs in an intermediate language, the hardware accelerator including a accelerator of a Java processor for the execution of intermediate language instructions.

93. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an intermediate language accelerator chip, operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory, the accelerator chip being adapted to run at least portions of programs in an intermediate language, wherein some instructions generate a callback and get executed on the processor chip.

94. The system of claim 93 wherein a system of registers is used for transferring information between the SoC and accelerator for callbacks.

95. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an intermediate language accelerator chip, operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory, wherein the use of the accelerator chip is in a cell phone or mobile handheld device.

96. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an intermediate language accelerator chip, operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory wherein the accelerator is stacked on the SoC in the same package

97. System of claim 96 wherein the use of the accelerator chip is in a cell phone or mobile handheld device.

98. A system comprising:

at least one memory;

a processor chip operably connected to the at least one memory; and

an intermediate language accelerator chip, operably connected to the at least one memory, memory access of the processor chip to the at least one memory being sent through the accelerator chip, the accelerator chip having direct access to the at least one memory wherein the accelerator is stacked with one or more memory in the same package.

99. System of claim 98 wherein the use of the accelerator chip is in a cell phone or mobile handheld device.