Thermal processing for three dimensional circuits

• US 20030025176A1
• Filed: 09/26/2002
• Published: 02/06/2003
• Est. Priority Date: 08/14/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Calvin K. Li, James M. Cleeves, Johan N. Knall, Michael A. Vyvoda, Vivek Subramanian
• Inventors: Cleeves, James M., Subramanian, Vivek, Li, Calvin K., Knall, N. Johan, Vyvoda, Michael A.
• Granted Patent: US 6,770,939 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

Claims

1. An apparatus comprising:

a substrate;

a circuit comprising n circuit levels formed over the substrate from a first level to a nth level, wherein

n is greater than one, and

each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously.

2. The apparatus of claim 1, wherein each circuit level comprises a crystalline structure and the material parameter is crystal growth.

3. The apparatus of claim 1, wherein each circuit level comprises a polycrystalline structure and the material parameter is grain growth.

4. The apparatus of claim 1, wherein the material parameter comprises microcrystalline grain growth.

5. The apparatus of claim 1, wherein the material parameter comprises amorphous material grain growth.

6. The apparatus of claim 1, wherein each circuit level comprises a material including a dopant profile therein and the material parameter is dopant diffusion.

7. The apparatus of claim 1, wherein each circuit level comprises a metal silicide and the material parameter is a silicide resistance value.

8. The apparatus of claim 1, wherein each circuit level comprises an oxidative species and the material parameter is degree of oxidation.

9. The apparatus of claim 1, wherein each circuit level comprises an ordered material having a level of defects and the material parameter is degree of defect annealing.

10. The apparatus of claim 1, where each circuit level comprises a material having a first phase and the material parameter change is a phase change from the first phase to a different second phase.

11. The apparatus of claim 1, wherein the material parameter is resistivity.

12. The apparatus of claim 1, wherein the material parameter is diode leakage.

13. An apparatus comprising:

a circuit comprising a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

14. The apparatus of claim 13, wherein each circuit level comprises a crystalline structure and a material parameter is crystal growth.

15. The apparatus of claim 13, wherein each circuit level comprises a polycrystalline structure and a material parameter is grain growth.

16. The apparatus of claim 13, wherein a material parameter comprises microcrystalline grain growth.

17. The apparatus of claim 13, wherein a material parameter comprises amorphous material grain growth.

18. The apparatus of claim 13, wherein each circuit level comprises a material including a dopant profile therein and a material parameter is dopant diffusion.

19. The apparatus of claim 13, wherein each circuit level comprises a metal silicide and a material parameter is a silicide resistance value.

20. The apparatus of claim 13, wherein each circuit level comprises an oxidative species and a material parameter is degree of oxidation.

21. The apparatus of claim 13, wherein each circuit level comprises an ordered material having a level of defects and a material parameter is degree of defect annealing.

22. The apparatus of claim 13, where each circuit level comprises a material having a first phase and a material parameter change is a phase change from the first phase to a different second phase.

23. The apparatus of claim 13, wherein a material parameter comprises resistivity.

24. The apparatus of claim 13, wherein each circuit level comprises a diode and a material parameter comprises diode leakage.