Timing recovery in data communication circuits

• US 20030026369A1
• Filed: 07/31/2002
• Published: 02/06/2003
• Est. Priority Date: 08/02/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Curran, Philip, Molina Navarro, Alberto, Murray, Carl Damien
• Granted Patent: US 7,519,137 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/0335 Gardner detector

Abstract

In a 1000 BASE-T transceiver, a timing error detector (TED, 5) receives its inputs directly from the output of an ADC (2) and from a decision device (4). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC (2) are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED, 5) does not take inputs from the FFE (3) there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.

Claims

1. A timing recovery circuit for a data communication transceiver, the recovery circuit comprising a timing error detector (TED) providing an input to an oscillator via a loop filter, characterized in that,

the timing error detector (TED) comprises means for performing both decision directed (DD) and non decision directed (NDD) recovery, and

the TED is decoupled from a feed forward equalizer.

2. A timing recovery circuit as claimed in claim 1, wherein the circuit comprises means for providing an input to the TED solely from an analog to digital converter (ADC) for NDD recovery.

3. A timing recovery circuit as claimed in claim 1, wherein the circuit comprises means for providing an input to the TED (5) from both an analog to digital converter (ADC) and from a decision device for DD recovery.

4. A timing recovery circuit as claimed in claim 3, wherein the circuit comprises means for performing timing recovery in the following stages:

firstly a NDD stage in which the TED input is solely from the ADC,

a second stage for acquiring the remote scrambler and predicting symbols, and

a third, DD, stage during which the TED has inputs from both the ADC and from a decision device for locally predicting symbols.

5. A timing recovery circuit as claimed in claim 4, wherein the circuit comprises means for switching to the third stage only when timing reaches an acceptable level, with the scramblers locked.

6. A timing recovery circuit as claimed in claim 4, wherein the ADC comprises means for over-sampling during the first stage.

7. A timing recovery circuit as claimed in claim 6, wherein the over-sampling rate is twice the symbol rate.

8. A timing recovery circuit as claimed in claim 1, wherein the circuit further comprises means for scaling output of the timing error detector by a varying correction factor based on cable length.

9. A timing recovery circuit as claimed in claim 8, wherein the correction factor is determined according to AGC gain value during start-up without echo or NEXT.

10. A data communications transceiver comprising a timing recovery circuit as claimed in any preceding claim.